🚧 CONSTRUCTING 🚧

The CELLRV32 RISC-V Processor

Note: this project is referred from [The NEORV32 Processor](https://github.com/stnolting/neorv32.git) by Stephan Nolting.

1. Overview
   • Key Features
   • Project Status
   • Progress
2. Features
3. FPGA Implementation Results
4. Performance
5. Software Framework & Tooling
6. Getting Started

1. Overview

The CELLRV32 Processor is a customizable microcontroller-like system on chip (SoC) built around the CELLRV32 RISC-V CPU and written in platform-independent SystemVerilog. The processor is intended as know about specific arrangement of registers, ALUs, finite state machines (FSMs), memories, and other logic building blocks (microarchitecture) needed to implement an RISC-V architecture and building blocks from theory of operation to combinational and sequential circuits for the internal IPs. The project is intended to work out of the box and targets FPGA / RISC-V beginners and amateurs.

Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory accesses are properly acknowledged and that all invalid/malformed instructions are always detected as such. Whenever an unexpected situation occurs the application software is informed via precise and resumable hardware exceptions.

Key Features

• all-in-one package: CPU + SoC + Software Framework & Tooling
• extensive configuration options for adapting the processor to the requirements of the application
• aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
• FPGA friendly (e.g. all internal memories can be mapped to block RAM - including the CPU's register file)
• optimized for high clock frequencies to ease integration / timing closure
• from zero to "hello world!" - completely open source and documented
• easy to use even for FPGA / RISC-V starters – intended to work out of the box

Project Status

	Repository & Status
GitHub Pages (docs)
Processor (SoC) verification
FPGA implementations
Prebuilt GCC toolchains
RISCOF core verification

Progress

• Stage 1: The purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.

• Stage 2: Designed a custom RISC-V MCU-class with lightweight snooping-based cache coherence and heterogeneous acceleration: integrating multiple CPU cores, vector extensions, scratchpad memory, DMA engine, an INT16/INT32 NPU, and a lightweight programmable GPU with parallel compute cores.