Integration testing using embedded-test #154
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LGTM, if you'd like to mark as ready. |
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This PR adds the basic structure for integration tests that run on actual hardware utilizing the embedded-test harness. This makes it possible to do "hardware-in-the-loop" testing very easily, thus being able to see if the hardware is behaving as the HAL expects and vice versa.
Marking this as a draft PR as I'd like to finish up the GPIO tests, ask some questions regarding hardware/HAL behaviour and find a good way to structure the tests for different hardware. While also checking if this sort of thing is desirable.
I am developing this against an STM32F401RETx, but it should be possible to transplant most of the logic to other hardware. Key differences being which GPIO pins should be used for the self-connected wires.