L4+ support (focussed on L4P5 / L4Q5)

Cargo.toml

@@ -22,7 +22,7 @@ cortex-m = "0.7.3"
 # Peripheral Access Crates
 stm32f3 = { version = "0.15.1", optional = true }
 stm32f4 = { version = "0.15.1", optional = true }
-stm32l4 = { version = "0.15.1", optional = true }
+stm32l4 = { path = "../stm32-rs/stm32l4", optional = true }
 stm32l5 = { version = "0.15.1", optional = true }
 stm32g0 = { version = "0.15.1", optional = true }
 stm32g4 = { version = "0.15.1", optional = true }
@@ -107,6 +107,8 @@ l4x5 = ["stm32l4/stm32l4x5", "l4"]
 l4x6 = ["stm32l4/stm32l4x6", "l4"]
 # todo: Handle l4+ (P, R, S, Q)
 
+l4p5 = ["stm32l4/stm32l4p5", "l4p"]
+
 # [L5](https://docs.rs/crate/stm32l5/latest/source/Cargo.toml)
 l552 = ["stm32l5/stm32l552", "l5"]
 l562 = ["stm32l5/stm32l562", "l5"]
@@ -165,6 +167,7 @@ embedded_hal = ["embedded-hal", "nb"]
 f3 = []
 f4 = []
 l4 = []
+l4p = []
 l5 = []
 g0 = []
 g4 = []

src/adc.rs

@@ -870,15 +870,15 @@ macro_rules! hal {
 
                 // L44 RM, Table 41. "DMA1 requests for each channel
                 // todo: DMA2 support.
-                #[cfg(any(feature = "f3", feature = "l4"))]
+                #[cfg(any(feature = "f3", all(feature = "l4", not(feature = "l4plus"))))]
                 let dma_channel = match self.device {
                     AdcDevice::One => DmaInput::Adc1.dma1_channel(),
                     AdcDevice::Two => DmaInput::Adc2.dma1_channel(),
                     _ => panic!("DMA on ADC beyond 2 is not supported. If it is for your MCU, please submit an issue \
                 or PR on Github.")
                 };
 
-                #[cfg(feature = "l4")]
+                #[cfg(all(feature = "l4", not(feature = "l4plus")))]
                 match self.device {
                     AdcDevice::One => dma.channel_select(DmaInput::Adc1),
                     AdcDevice::Two => dma.channel_select(DmaInput::Adc2),

src/clocks/baseline.rs

@@ -10,7 +10,7 @@ use crate::{
     util::rcc_en_reset,
 };
 
-#[cfg(any(feature = "l4", feature = "l5", feature = "wb", feature = "g4"))]
+#[cfg(any(feature = "l4", feature = "l4p", feature = "l5", feature = "wb", feature = "g4"))]
 use crate::pac::CRS;
 
 use cfg_if::cfg_if;
@@ -31,7 +31,7 @@ pub enum Clk48Src {
     Msi = 0b11,
 }
 
-#[cfg(any(feature = "l4", feature = "l5", feature = "wb", feature = "g4"))]
+#[cfg(any(feature = "l4", feature = "l4p", feature = "l5", feature = "wb", feature = "g4"))]
 #[derive(Clone, Copy)]
 #[repr(u8)]
 /// Select the SYNC signal source. Sets the CRS_CFGR register, SYNCSRC field.
@@ -80,7 +80,7 @@ impl PllSrc {
     }
 }
 
-#[cfg(any(feature = "l4", feature = "l5", feature = "wb", feature = "wl"))]
+#[cfg(any(feature = "l4", feature = "l4p", feature = "l5", feature = "wb", feature = "wl"))]
 #[derive(Clone, Copy, PartialEq)]
 #[repr(u8)]
 /// Select the system clock used when exiting Stop mode. Sets RCC_CFGR register, STOPWUCK field.
@@ -266,6 +266,8 @@ impl Default for PllCfg {
             divn: 64,
             #[cfg(feature = "wl")]
             divn: 24,
+            #[cfg(feature = "l4p")]
+            divn: 16,
             #[cfg(not(feature = "wb"))]
             divr: Pllr::Div2,
             #[cfg(feature = "wb")]
@@ -568,7 +570,7 @@ pub struct Clocks {
     #[cfg(not(any(feature = "g0", feature = "wl")))]
     /// Enable the HSI48. For L4, this is only applicable for some devices.
     pub hsi48_on: bool,
-    #[cfg(any(feature = "l4", feature = "l5", feature = "wb", feature = "wl"))]
+    #[cfg(any(feature = "l4", feature = "l4p", feature = "l5", feature = "wb", feature = "wl"))]
     /// Select the input source to use after waking up from `stop` mode. Eg HSI or MSI.
     pub stop_wuck: StopWuck,
     #[cfg(feature = "wb")]
@@ -577,7 +579,7 @@ pub struct Clocks {
     #[cfg(not(any(feature = "g0", feature = "g4", feature = "wl")))]
     /// SAI1 kernel clock source selection
     pub sai1_src: SaiSrc,
-    #[cfg(feature = "g4")]
+    #[cfg(any(feature = "g4", feature = "l4p"))]
     /// Range 1 boost mode: Used to increase regulator voltage to 1.28v, for when system
     /// clock frequency is up to 170Mhz. Defaults to true.
     pub boost_mode: bool,
@@ -619,7 +621,7 @@ impl Clocks {
         }
 
         cfg_if! {
-            if #[cfg(feature = "g4")] {
+            if #[cfg(any(feature = "g4", feature = "l4p"))] {
                 if self.boost_mode {
                     // The sequence to switch from Range1 normal mode to Range1 boost mode is:
                     // 1. The system clock must be divided by 2 using the AHB prescaler before switching to a
@@ -1066,7 +1068,7 @@ impl Clocks {
                         while rcc.cr.read().hserdy().bit_is_clear() {}
                     }
                     PllSrc::Hsi => {
-                        #[cfg(any(feature = "l4", feature = "l5"))]
+                        #[cfg(any(feature = "l4", feature = "l4p", feature = "l5"))]
                         // Generally reverts to MSI (see note below)
                         if let StopWuck::Msi = self.stop_wuck {
                             rcc.cr.modify(|_, w| w.hsion().set_bit());
@@ -1387,6 +1389,9 @@ impl Clocks {
         #[cfg(feature = "l4")]
         let max_clock = 80_000_000;
 
+        #[cfg(feature = "l4p")]
+        let max_clock = 120_000_000;
+
         #[cfg(feature = "l5")]
         let max_clock = 110_000_000;
 
@@ -1497,13 +1502,13 @@ impl Default for Clocks {
             security_system: false,
             #[cfg(not(any(feature = "g0", feature = "wl")))]
             hsi48_on: false,
-            #[cfg(any(feature = "l4", feature = "l5", feature = "wb", feature = "wl"))]
+            #[cfg(any(feature = "l4", feature = "l4p", feature = "l5", feature = "wb", feature = "wl"))]
             stop_wuck: StopWuck::Msi,
             #[cfg(feature = "wb")]
             rf_wakeup_src: RfWakeupSrc::Lse,
             #[cfg(not(any(feature = "g0", feature = "g4", feature = "wl")))]
             sai1_src: SaiSrc::Pllp,
-            #[cfg(feature = "g4")]
+            #[cfg(any(feature = "g4", feature = "l4p"))]
             boost_mode: true,
         }
     }

src/clocks/mod.rs

@@ -17,7 +17,7 @@ cfg_if::cfg_if! {
     if #[cfg(any(feature = "f3", feature = "f4"))] {
         mod f;
         pub use f::*;
-    } else if #[cfg(any(feature = "l4", feature = "l5", feature = "g0", feature = "g4", feature = "wb", feature = "wl"))] {
+    } else if #[cfg(any(feature = "l4", feature = "l4p", feature = "l5", feature = "g0", feature = "g4", feature = "wb", feature = "wl"))] {
         mod baseline;
         pub use baseline::*;
     } else if #[cfg(feature = "u5")] {

src/crc.rs

@@ -20,7 +20,7 @@ impl CrcExt for CRC {
             if #[cfg(feature = "f3")] {
                 rcc.ahbenr.modify(|_, w| w.crcen().set_bit());
                 // F3 doesn't appear to have a crcrst field in `ahbrstr`, per RM.
-            } else if #[cfg(any(feature = "l4", feature = "wb"))] {
+            } else if #[cfg(any(feature = "l4", feature = "l4p", feature = "wb"))] {
                 rcc.ahb1enr.modify(|_, w| w.crcen().set_bit());
                 rcc.ahb1rstr.modify(|_, w| w.crcrst().set_bit());
                 rcc.ahb1rstr.modify(|_, w| w.crcrst().clear_bit());
@@ -157,7 +157,7 @@ impl Crc {
             ///
             /// The IDR is not involved with CRC calculation.
             pub fn set_idr(&mut self, value: u8) {
-                self.reg.idr.write(|w| w.idr().bits(value));
+                self.reg.idr.write(|w| unsafe { w.idr().bits(value) });
             }
         }
     }

src/dac.rs

@@ -347,13 +347,13 @@ where
     {
         let (ptr, len) = (buf.as_ptr(), buf.len());
 
-        #[cfg(any(feature = "f3", feature = "l4"))]
+        #[cfg(any(feature = "f3", all(feature = "l4", not(feature = "l4plus"))))]
         let dma_channel = match dac_channel {
             DacChannel::C1 => DmaInput::Dac1Ch1.dma1_channel(),
             DacChannel::C2 => DmaInput::Dac1Ch2.dma1_channel(),
         };
 
-        #[cfg(feature = "l4")]
+        #[cfg(all(feature = "l4", not(feature = "l4plus")))]
         match dac_channel {
             DacChannel::C1 => dma.channel_select(DmaInput::Dac1Ch1),
             DacChannel::C2 => dma.channel_select(DmaInput::Dac1Ch2),