Skip to content

Commit d5acd42

Browse files
MrSidimsMrSidims
authored
Update SPV_INTEL_long_composites tokens (KhronosGroup#375)
Signed-off-by: Sidorov, Dmitry <[email protected]>
1 parent cca08c6 commit d5acd42

File tree

10 files changed

+38
-14
lines changed

10 files changed

+38
-14
lines changed

‎include/spirv/unified1/spirv.bf

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1197,7 +1197,7 @@ namespace Spv
11971197
GroupNonUniformRotateKHR = 6026,
11981198
AtomicFloat32AddEXT = 6033,
11991199
AtomicFloat64AddEXT = 6034,
1200-
LongConstantCompositeINTEL = 6089,
1200+
LongCompositesINTEL = 6089,
12011201
OptNoneINTEL = 6094,
12021202
AtomicFloat16AddEXT = 6095,
12031203
DebugInfoModuleINTEL = 6114,
@@ -2094,6 +2094,7 @@ namespace Spv
20942094
OpTypeStructContinuedINTEL = 6090,
20952095
OpConstantCompositeContinuedINTEL = 6091,
20962096
OpSpecConstantCompositeContinuedINTEL = 6092,
2097+
OpCompositeConstructContinuedINTEL = 6096,
20972098
OpConvertFToBF16INTEL = 6116,
20982099
OpConvertBF16ToFINTEL = 6117,
20992100
OpControlBarrierArriveINTEL = 6142,

‎include/spirv/unified1/spirv.core.grammar.json

Lines changed: 17 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9564,7 +9564,7 @@
95649564
"operands" : [
95659565
{ "kind" : "IdRef", "quantifier" : "*", "name" : "'Member 0 type', +\n'member 1 type', +\n..." }
95669566
],
9567-
"capabilities" : [ "LongConstantCompositeINTEL" ],
9567+
"capabilities" : [ "LongCompositesINTEL" ],
95689568
"version" : "None"
95699569
},
95709570
{
@@ -9574,7 +9574,7 @@
95749574
"operands" : [
95759575
{ "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" }
95769576
],
9577-
"capabilities" : [ "LongConstantCompositeINTEL" ],
9577+
"capabilities" : [ "LongCompositesINTEL" ],
95789578
"version" : "None"
95799579
},
95809580
{
@@ -9584,9 +9584,21 @@
95849584
"operands" : [
95859585
{ "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" }
95869586
],
9587-
"capabilities" : [ "LongConstantCompositeINTEL" ],
9587+
"capabilities" : [ "LongCompositesINTEL" ],
95889588
"version" : "None"
95899589
},
9590+
{
9591+
"opname" : "OpCompositeConstructContinuedINTEL",
9592+
"class" : "Composite",
9593+
"opcode" : 6096,
9594+
"operands" : [
9595+
{ "kind" : "IdResultType" },
9596+
{ "kind" : "IdResult" },
9597+
{ "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" }
9598+
],
9599+
"capabilities" : [ "LongCompositesINTEL" ],
9600+
"version": "None"
9601+
},
95909602
{
95919603
"opname" : "OpConvertFToBF16INTEL",
95929604
"class" : "Conversion",
@@ -16224,9 +16236,9 @@
1622416236
"version" : "None"
1622516237
},
1622616238
{
16227-
"enumerant" : "LongConstantCompositeINTEL",
16239+
"enumerant" : "LongCompositesINTEL",
1622816240
"value" : 6089,
16229-
"extensions" : [ "SPV_INTEL_long_constant_composite" ],
16241+
"extensions" : [ "SPV_INTEL_long_composites" ],
1623016242
"version" : "None"
1623116243
},
1623216244
{

‎include/spirv/unified1/spirv.cs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1196,7 +1196,7 @@ public enum Capability
11961196
GroupNonUniformRotateKHR = 6026,
11971197
AtomicFloat32AddEXT = 6033,
11981198
AtomicFloat64AddEXT = 6034,
1199-
LongConstantCompositeINTEL = 6089,
1199+
LongCompositesINTEL = 6089,
12001200
OptNoneINTEL = 6094,
12011201
AtomicFloat16AddEXT = 6095,
12021202
DebugInfoModuleINTEL = 6114,
@@ -2093,6 +2093,7 @@ public enum Op
20932093
OpTypeStructContinuedINTEL = 6090,
20942094
OpConstantCompositeContinuedINTEL = 6091,
20952095
OpSpecConstantCompositeContinuedINTEL = 6092,
2096+
OpCompositeConstructContinuedINTEL = 6096,
20962097
OpConvertFToBF16INTEL = 6116,
20972098
OpConvertBF16ToFINTEL = 6117,
20982099
OpControlBarrierArriveINTEL = 6142,

‎include/spirv/unified1/spirv.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1196,7 +1196,7 @@ typedef enum SpvCapability_ {
11961196
SpvCapabilityGroupNonUniformRotateKHR = 6026,
11971197
SpvCapabilityAtomicFloat32AddEXT = 6033,
11981198
SpvCapabilityAtomicFloat64AddEXT = 6034,
1199-
SpvCapabilityLongConstantCompositeINTEL = 6089,
1199+
SpvCapabilityLongCompositesINTEL = 6089,
12001200
SpvCapabilityOptNoneINTEL = 6094,
12011201
SpvCapabilityAtomicFloat16AddEXT = 6095,
12021202
SpvCapabilityDebugInfoModuleINTEL = 6114,
@@ -2090,6 +2090,7 @@ typedef enum SpvOp_ {
20902090
SpvOpTypeStructContinuedINTEL = 6090,
20912091
SpvOpConstantCompositeContinuedINTEL = 6091,
20922092
SpvOpSpecConstantCompositeContinuedINTEL = 6092,
2093+
SpvOpCompositeConstructContinuedINTEL = 6096,
20932094
SpvOpConvertFToBF16INTEL = 6116,
20942095
SpvOpConvertBF16ToFINTEL = 6117,
20952096
SpvOpControlBarrierArriveINTEL = 6142,
@@ -2813,6 +2814,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
28132814
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
28142815
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
28152816
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
2817+
case SpvOpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break;
28162818
case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
28172819
case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
28182820
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;

‎include/spirv/unified1/spirv.hpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1192,7 +1192,7 @@ enum Capability {
11921192
CapabilityGroupNonUniformRotateKHR = 6026,
11931193
CapabilityAtomicFloat32AddEXT = 6033,
11941194
CapabilityAtomicFloat64AddEXT = 6034,
1195-
CapabilityLongConstantCompositeINTEL = 6089,
1195+
CapabilityLongCompositesINTEL = 6089,
11961196
CapabilityOptNoneINTEL = 6094,
11971197
CapabilityAtomicFloat16AddEXT = 6095,
11981198
CapabilityDebugInfoModuleINTEL = 6114,
@@ -2086,6 +2086,7 @@ enum Op {
20862086
OpTypeStructContinuedINTEL = 6090,
20872087
OpConstantCompositeContinuedINTEL = 6091,
20882088
OpSpecConstantCompositeContinuedINTEL = 6092,
2089+
OpCompositeConstructContinuedINTEL = 6096,
20892090
OpConvertFToBF16INTEL = 6116,
20902091
OpConvertBF16ToFINTEL = 6117,
20912092
OpControlBarrierArriveINTEL = 6142,
@@ -2809,6 +2810,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
28092810
case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
28102811
case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
28112812
case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
2813+
case OpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break;
28122814
case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
28132815
case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
28142816
case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;

‎include/spirv/unified1/spirv.hpp11

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1192,7 +1192,7 @@ enum class Capability : unsigned {
11921192
GroupNonUniformRotateKHR = 6026,
11931193
AtomicFloat32AddEXT = 6033,
11941194
AtomicFloat64AddEXT = 6034,
1195-
LongConstantCompositeINTEL = 6089,
1195+
LongCompositesINTEL = 6089,
11961196
OptNoneINTEL = 6094,
11971197
AtomicFloat16AddEXT = 6095,
11981198
DebugInfoModuleINTEL = 6114,
@@ -2086,6 +2086,7 @@ enum class Op : unsigned {
20862086
OpTypeStructContinuedINTEL = 6090,
20872087
OpConstantCompositeContinuedINTEL = 6091,
20882088
OpSpecConstantCompositeContinuedINTEL = 6092,
2089+
OpCompositeConstructContinuedINTEL = 6096,
20892090
OpConvertFToBF16INTEL = 6116,
20902091
OpConvertBF16ToFINTEL = 6117,
20912092
OpControlBarrierArriveINTEL = 6142,
@@ -2809,6 +2810,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
28092810
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
28102811
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
28112812
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
2813+
case Op::OpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break;
28122814
case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
28132815
case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
28142816
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;

‎include/spirv/unified1/spirv.json

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1172,7 +1172,7 @@
11721172
"GroupNonUniformRotateKHR": 6026,
11731173
"AtomicFloat32AddEXT": 6033,
11741174
"AtomicFloat64AddEXT": 6034,
1175-
"LongConstantCompositeINTEL": 6089,
1175+
"LongCompositesINTEL": 6089,
11761176
"OptNoneINTEL": 6094,
11771177
"AtomicFloat16AddEXT": 6095,
11781178
"DebugInfoModuleINTEL": 6114,
@@ -2088,6 +2088,7 @@
20882088
"OpTypeStructContinuedINTEL": 6090,
20892089
"OpConstantCompositeContinuedINTEL": 6091,
20902090
"OpSpecConstantCompositeContinuedINTEL": 6092,
2091+
"OpCompositeConstructContinuedINTEL": 6096,
20912092
"OpConvertFToBF16INTEL": 6116,
20922093
"OpConvertBF16ToFINTEL": 6117,
20932094
"OpControlBarrierArriveINTEL": 6142,

‎include/spirv/unified1/spirv.lua

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1154,7 +1154,7 @@ spv = {
11541154
GroupNonUniformRotateKHR = 6026,
11551155
AtomicFloat32AddEXT = 6033,
11561156
AtomicFloat64AddEXT = 6034,
1157-
LongConstantCompositeINTEL = 6089,
1157+
LongCompositesINTEL = 6089,
11581158
OptNoneINTEL = 6094,
11591159
AtomicFloat16AddEXT = 6095,
11601160
DebugInfoModuleINTEL = 6114,
@@ -2030,6 +2030,7 @@ spv = {
20302030
OpTypeStructContinuedINTEL = 6090,
20312031
OpConstantCompositeContinuedINTEL = 6091,
20322032
OpSpecConstantCompositeContinuedINTEL = 6092,
2033+
OpCompositeConstructContinuedINTEL = 6096,
20332034
OpConvertFToBF16INTEL = 6116,
20342035
OpConvertBF16ToFINTEL = 6117,
20352036
OpControlBarrierArriveINTEL = 6142,

‎include/spirv/unified1/spirv.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1154,7 +1154,7 @@
11541154
'GroupNonUniformRotateKHR' : 6026,
11551155
'AtomicFloat32AddEXT' : 6033,
11561156
'AtomicFloat64AddEXT' : 6034,
1157-
'LongConstantCompositeINTEL' : 6089,
1157+
'LongCompositesINTEL' : 6089,
11581158
'OptNoneINTEL' : 6094,
11591159
'AtomicFloat16AddEXT' : 6095,
11601160
'DebugInfoModuleINTEL' : 6114,
@@ -2030,6 +2030,7 @@
20302030
'OpTypeStructContinuedINTEL' : 6090,
20312031
'OpConstantCompositeContinuedINTEL' : 6091,
20322032
'OpSpecConstantCompositeContinuedINTEL' : 6092,
2033+
'OpCompositeConstructContinuedINTEL' : 6096,
20332034
'OpConvertFToBF16INTEL' : 6116,
20342035
'OpConvertBF16ToFINTEL' : 6117,
20352036
'OpControlBarrierArriveINTEL' : 6142,

‎include/spirv/unified1/spv.d

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1199,7 +1199,7 @@ enum Capability : uint
11991199
GroupNonUniformRotateKHR = 6026,
12001200
AtomicFloat32AddEXT = 6033,
12011201
AtomicFloat64AddEXT = 6034,
1202-
LongConstantCompositeINTEL = 6089,
1202+
LongCompositesINTEL = 6089,
12031203
OptNoneINTEL = 6094,
12041204
AtomicFloat16AddEXT = 6095,
12051205
DebugInfoModuleINTEL = 6114,
@@ -2096,6 +2096,7 @@ enum Op : uint
20962096
OpTypeStructContinuedINTEL = 6090,
20972097
OpConstantCompositeContinuedINTEL = 6091,
20982098
OpSpecConstantCompositeContinuedINTEL = 6092,
2099+
OpCompositeConstructContinuedINTEL = 6096,
20992100
OpConvertFToBF16INTEL = 6116,
21002101
OpConvertBF16ToFINTEL = 6117,
21012102
OpControlBarrierArriveINTEL = 6142,

0 commit comments

Comments
 (0)