Pmod bridge: Fix the disabled bottom row bug #60
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…gn comment The comment is attached to the Pmod bridge object in order to hide it when the hierarchy is closed The readme was edited to remove illegal characters that prevent the set_property tcl command from evaluating properly (primarily the quotes) Newlines were inserted to ensure that the text fits in the window (a standard width should be established)
Originally, some ports shared the FPGA-side ports with other interfaces. This led to highly-confusing enablement dependency conditions. Splitting out all of the ports so that each interface has its own set makes it so that the dependency conditions are only required at the interface level instead of also at the port level.
Refer to Xilinx PG090's AXI clock frequency requirements
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In version 1.3 of the Pmod Bridge, this fixes the issue where disabling the top or bottom row interface causes the ports to which the board constraints are applied to not be created, resulting in implementation errors. Version 1.0 of the bridge is not changed, and should be replaced in Pmod IPs and hierarchies going forward. The IP was repackaged and tested in version 2021.1 of the tools with the Pmod NAV and Pmod AD1 hierarchies, but it should also be tested in 2019.1 with UART and I2C hierarchies and a repackaged Pmod IP to ensure we have backward-compatible support for that version.
Incidentally, a parameter for optional I2C pullups on the bottom row interface is added, as well as some general refactoring of pmod_concat and the ports and interfaces sections of component.xml, in order to clean up some of the port/interface enablement dependency logic. FPGA-side interface mode "None" is removed, and GPIO interfaces or manually constrained external ports should be favored in the use cases where this might have been handy.
The Pmod AD1 hierarchy also has its readme added as a BD comment, a feature that should be rolled out into other hierarchies.
Sources for testing can be obtained from the branch's source ZIP