dvi2rgb fixes for cadence #81
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…ut side and assign the new signals
…, which is what is happening in the FPGA any way
added 2 commits
April 11, 2024 08:55
… successfully in incisive/cadence
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The code did not work in cadence. Some of the code was not explict enough and cadence flags a exceptions of a increment rolls over its maximum, in fpga land this is modulo, so that is what the code has been changed to.
This code has been verified in simulation and synthesis.