An FPGA-accelerated digital signal processing (DSP) pipeline converting raw radio telescope data from EPFL’s Very Elegant Galactic Antenna (VEGA) into calibrated spectra. The pipeline extracts Doppler-shifted 21 cm hydrogen line peaks to measure the rotation speed of the Milky Way. Designed for the Xilinx Zynq-7020 on a PYNQ-Z2 board, this project exemplifies hardware/software co-design with latency/energy Pareto-optimal tradeoffs across 10 FFT configurations.
flowchart LR
A[Raw ADC Data] -->|DMA Transfer| B(FFT Accelerator)
B --> C[Power Spectrum Generation]
C --> D[Smoothing & Peak Detection]
D --> E[Hydrogen Line Extraction]
E --> F[Metrics Reporting]
Hydrogen is the most abundant element in our galaxy, emitting a characteristic 21 cm wavelength due to spin-flip transitions. By detecting Doppler-shifted peaks of these emissions, we measure the rotational velocities of different galactic arms. This project aims to perform efficient real-time processing on large radio data sets captured by the VEGA telescope at EPFL, minimizing both latency and energy consumption.
This project implements a sophisticated, highly configurable, FPGA-accelerated digital signal processing (DSP) pipeline specifically designed for astronomical radio signal analysis. Leveraging advanced hardware/software co-design methodologies, it efficiently transforms raw radio telescope data from EPFL’s Very Elegant Galactic Antenna (VEGA) into precise spectral data capable of extracting Doppler-shifted 21 cm hydrogen emission peaks. The system exploits multi-resolution Fast Fourier Transform (FFT) architectures (ranging from 1k to 524k points), batch DMA transfers, custom FFT hardware accelerators, SIMD instructions, and parallel processing on ARM Cortex-A9 processors, combined with zero-copy DMA memory management to achieve latency and energy efficiency. Comprehensive real-time profiling via XADC energy measurement, deterministic SNR validation (>70 dB), and modular, dynamically reconfigurable FPGA designs ensure an optimal trade-off between latency, energy consumption, hardware resource utilization, and spectral accuracy, positioning the design firmly on the Pareto frontier of performance and efficiency.
The signal processing pipeline ncludes:
- Loading of raw input data and calibration gains.
- Segmentation according to selected FFT resolution (1k–524k points).
- Hanning windowing with 75% overlap.
- FFT execution (performed 40,000 times per dataset).
- Averaging power spectrum calculation (Welch’s method).
- Spectrum normalization.
- Moving average, spike smoothing, and Gaussian smoothing.
- Calibration with antenna gains.
- Peak detection corresponding to galactic arms.
- Calculation of relative velocities based on Doppler shift.
The design strategically balances the following metrics:
- Latency: Total execution time.
- Energy Consumption: Efficiency measured directly on the board.
- Hardware Resources: DSP, LUT, BRAM, FF usage on FPGA.
- Resolution: Frequency accuracy.
- Flexibility: Support for multiple FFT configurations.
- SNR: Signal quality maintained above 70 dB.
sequenceDiagram
participant Host as ARM Cortex-A9
participant DMA as CMA Allocator
participant FPGA as Custom FFT IP
participant XADC as Power Ranger
participant SW as Signal Processing
Host->>DMA: Allocate contiguous buffer
Host->>FPGA: DMA Transfer & IRQ
FPGA->>Host: Interrupt on batch completion
Host->>XADC: Sample energy
Host->>SW: Welch PSD & smoothing
SW->>Host: Peak results & metrics
Directory Layout
radioastro.cpp— Application driversignal_processing.cpp/h— DSP kernelsCFFTDriver.*/CAccelDriver.*— DMA/IRQ driversadder.c— Kernel module exampleMakefile+ TCL scripts — Automated build flowdata_bin/— Raw samples, calibration filesscripts/clean,load,unload— Kernel module helpers
sudo ./radioastro \
-s data_bin/signal_data.bin \
-c 3 \
-o out_spectrum.bin \
-p metrics_mode3.csv
sudo ./run_all.shOutputs include detailed time/energy metrics and validation of SNR ≥ 70 dB.
Use included scripts for visual analysis:
python plot_res.py --file out.bin
python plot_timings.py -f metrics.csv- Runtime Configurability
- Efficient Welch PSD Computation
- Hardware DMA & FFT Pipelining
- Real-time Energy Metering (XADC)
- SIMD & Multi-Core Optimization
- Robust IRQ Handling
- Fixed-Point Arithmetic (Proposed)
- Model and add new kernels
- Dynamic FPGA reconfiguration
- Fixed-point DSP for resource savings
Project data and guidelines provided by EPFL Embedded Systems Laboratory (SEL) and the VEGA telescope team. Enjoy exploring the galaxy at FPGA speed!