@@ -14,8 +14,7 @@ extern CPU_state cpu;
1414#define NOP do {} while(0)
1515
1616enum {
17- TYPE_I , TYPE_U , TYPE_S ,
18- TYPE_N , TYPE_J
17+ TYPE_R , TYPE_I , TYPE_S , TYPE_B , TYPE_U , TYPE_J , TYPE_N
1918};
2019
2120#define src1R () do { *src1 = R(rs1); } while (0)
2726 BITS(i, 20, 20) << 11 | \
2827 BITS(i, 30, 21) << 1, 21);} while(0)
2928#define immS () do { *imm = (SEXT(BITS(i, 31, 25), 7) << 5) | BITS(i, 11, 7); } while(0)
30- #define immB () do { *imm = ( SEXT(BITS(i, 31, 31) << 12 | \
29+ #define immB () do { *imm = SEXT(BITS(i, 31, 31) << 12 | \
3130 BITS(i, 7, 7) << 11 | \
3231 BITS(i, 30, 25) << 5 | \
3332 BITS(i, 11, 8) << 1, 13);} while(0)
@@ -40,10 +39,10 @@ static void decode_operand(Decode *s, int *rd, uint64_t *src1, uint64_t *src2, u
4039 switch (type ) {
4140 case TYPE_R : src1R (); src2R (); break ;
4241 case TYPE_I : src1R (); immI (); break ;
43- case TYPE_U : immU (); break ;
44- case TYPE_J : immJ (); break ;
4542 case TYPE_S : src1R (); src2R (); immS (); break ;
4643 case TYPE_B : src1R (); src2R (); immB (); break ;
44+ case TYPE_U : immU (); break ;
45+ case TYPE_J : immJ (); break ;
4746 }
4847}
4948void decode_exec (Decode * s ){
@@ -116,8 +115,8 @@ void decode_exec(Decode *s){
116115 INSTPAT ("0000000 ????? ????? 101 ????? 01110 11" , srlw , R , R (rd ) = SEXT ((uint32_t )src1 >> (src2 & 0x1f ), 32 ));
117116 INSTPAT ("0100000 ????? ????? 101 ????? 01110 11" , sraw , R , R (rd ) = SEXT ((int32_t )src1 >> (src2 & 0x1f ), 32 ));
118117 // FENCE, FENCE.I
119- INSTPAT ("0000??? ????? 00000 000 00000 00011 11" , fence , I , NOP );
120- INSTPAT ("0000000 00000 00000 000 00000 00011 11" , fencei , I , NOP );
118+ INSTPAT ("0000??? ????? 00000 000 00000 00011 11" , fence , N , NOP );
119+ INSTPAT ("0000000 00000 00000 000 00000 00011 11" , fencei , N , NOP );
121120 // ECALL
122121 INSTPAT ("0000000 00001 00000 000 00000 11100 11" , ebreak , N , HALT (s -> pc , R (10 ))); // R(10) is $a0
123122 // CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI
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