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Doc: add mc and pl doc RISC-V Simulator CI #19: Commit 598e438 pushed by EmbroiderSnow
1m 25s main
main
1m 25s
feat: implement multi-cycle simulator RISC-V Simulator CI #18: Commit 51d19fe pushed by EmbroiderSnow
1m 40s main
main
1m 40s
refactor(main&makefile): support different processor model. RISC-V Simulator CI #17: Commit e02b088 pushed by EmbroiderSnow
1m 5s main
main
1m 5s
remove printf used to debug RISC-V Simulator CI #16: Commit ec38ab4 pushed by EmbroiderSnow
47s main
main
47s
fix(ftrace): sort the symbol table & target func name RISC-V Simulator CI #15: Commit 711d51a pushed by EmbroiderSnow
1m 30s main
main
1m 30s
Doc: add doc about features RISC-V Simulator CI #14: Commit 48b24c0 pushed by EmbroiderSnow
50s main
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50s
feat(ftrace): implement ftrace RISC-V Simulator CI #13: Commit 7212a60 pushed by EmbroiderSnow
49s main
main
49s
feat(ftrace): load and parse elf stab RISC-V Simulator CI #12: Commit 3579dcd pushed by EmbroiderSnow
46s main
main
46s
feat(trace): implement itrace RISC-V Simulator CI #11: Commit f9b9392 pushed by EmbroiderSnow
46s main
main
46s
feat(debug): import llvm to disasm the instruction RISC-V Simulator CI #10: Commit 665f6b6 pushed by EmbroiderSnow
44s main
main
44s
fix(ci): modify wrong test name RISC-V Simulator CI #9: Commit 29d4733 pushed by EmbroiderSnow
1m 39s main
main
1m 39s
Update main.yml RISC-V Simulator CI #8: Commit 949375e pushed by EmbroiderSnow
57s main
main
57s
feat(syscall): implement printf (syscall: write) RISC-V Simulator CI #7: Commit f884d75 pushed by EmbroiderSnow
1m 46s main
main
1m 46s
feat(decode): implement RV64M instructions RISC-V Simulator CI #6: Commit 468d792 pushed by EmbroiderSnow
1m 37s main
main
1m 37s
fix: remove upload sim RISC-V Simulator CI #5: Commit 944efc0 pushed by EmbroiderSnow
2m 17s main
main
2m 17s
fix: delete duplicate part of main.yml RISC-V Simulator CI #4: Commit 111a5bc pushed by EmbroiderSnow
7s main
main
7s
feat(ci): test matrix RISC-V Simulator CI #3: Commit 8eb47bf pushed by EmbroiderSnow
Failure main
main
Failure
Update main.yml RISC-V Simulator CI #2: Commit 411f31f pushed by EmbroiderSnow
49s main
main
49s
Create main.yml RISC-V Simulator CI #1: Commit 1230064 pushed by EmbroiderSnow
56s main
main
56s