feat: implement multi-cycle simulator

Author: EmbroiderSnow

sim/include/cpu.h

@@ -18,14 +18,17 @@ void init_cpu();
 void halt_trap(uint64_t pc, uint64_t code);
 
 // ------------ ISS SIM ------------
+
 void iss_cpu_exec();
 void iss_exec_once();
 
 // --------- Multi-cycle SIM ---------
+
 void mc_cpu_exec();
 void mc_exec_once();
 
 // ---------- Pipeline SIM -----------
+
 void pl_cpu_exec();
 void pl_exec_once();
 

sim/include/isa_decode.h

@@ -1,7 +1,11 @@
 #ifndef ISA_DECODE_H
 #define ISA_DECODE_H
 
-#include<stdint.h>
+#include <stdint.h>
+#include <pattern.h>
+#include <macro.h>
+#include <dbg.h>
+#include <memory.h>
 
 typedef enum {
     TYPE_R, TYPE_I, TYPE_S, TYPE_B, TYPE_U, TYPE_J, TYPE_N
@@ -38,4 +42,10 @@ void decode_operand(Decode *s, int *rd, uint64_t *src1, uint64_t *src2, uint64_t
                                 BITS(i, 30, 25) << 5 | \
                                 BITS(i, 11, 8) << 1, 13);} while(0)
 
+#define INSTPAT_INST(s) ((s)->inst)
+#define INSTPAT_MATCH(s, name, type, ... /* execute body */ ) { \
+  decode_operand(s, &rd, &src1, &src2, &imm, concat(TYPE_, type)); \
+  __VA_ARGS__ ; \
+}
+
 #endif

sim/include/mc_core.h

@@ -0,0 +1,23 @@
+#ifndef MC_CORE_H
+#define MC_CORE_H
+
+#include <isa_decode.h>
+
+typedef enum {
+    STAGE_IF,
+    STAGE_ID,
+    STAGE_EX,
+    STAGE_MEM,
+    STAGE_WB,
+    STAGE_DONE // check inst finish
+} Multi_Cycle_Stage;
+
+void mc_IF(Decode *s);
+void mc_ID(Decode *s);
+void mc_EX(Decode *s, uint64_t *alu_result);
+void mc_MEM(Decode *s, uint64_t alu_result, uint64_t *mem_result);
+void mc_WB(Decode *s, uint64_t alu_result, uint64_t mem_result);
+
+void push_stage(Decode *s, Multi_Cycle_Stage *stage);
+
+#endif

sim/include/memory.h

@@ -4,7 +4,7 @@
 #include <stdint.h>
 
 void load_image(char *filepath);
-void load_elf_symbols(char *filepath);
+void load_elf_symbols(const char *filepath);
 uint8_t* guest_to_host(uint64_t vaddr);
 uint32_t inst_fetch(uint64_t pc);
 uint64_t mem_read(uint64_t addr, int len);

sim/include/pattern.h

@@ -1,6 +1,8 @@
 #ifndef PATTERN_H
 #define PATTERN_H
 
+#include <dbg.h>
+
 // --- pattern matching mechanism ---
 __attribute__((always_inline))
 static inline void pattern_decode(const char *str, int len,

sim/src/cpu.c

@@ -1,5 +1,6 @@
 #include <common.h>
 #include <iss_core.h>
+#include <mc_core.h>
 #include <memory.h>
 #include <disasm.h>
 #include <macro.h>
@@ -12,13 +13,17 @@ extern LLVMDisasmContextRef disasm_ctx;
 int indentaton_level = 0;
 CPU_state cpu = {};
 static int running = 1;
+uint64_t global_cycle_count = 0;
+uint64_t ninst = 0;
 
 void init_cpu(){
     cpu.pc = MEM_BASE;
     memset(cpu.reg, 0, sizeof(cpu.reg));
     memset(cpu.csr, 0, sizeof(cpu.csr));
 }
 
+// ------------ ISS SIM ------------
+
 void iss_exec_once() {
     Decode s;
     s.pc   = cpu.pc;
@@ -40,6 +45,66 @@ void iss_cpu_exec() {
     }
 }
 
+// --------- Multi-cycle SIM ---------
+
+void mc_exec_once() {
+    // uint64_t record = global_cycle_count;
+    ++ninst;
+    Decode s;
+    Multi_Cycle_Stage stage = STAGE_IF;
+    uint64_t alu_result = 0;
+    uint64_t mem_result = 0;
+    while (stage != STAGE_DONE) {
+        switch (stage) {
+            case STAGE_IF:
+                mc_IF(&s);
+                if (itrace_enabled)
+                    handle_itrace(&s);
+                push_stage(&s, &stage);
+                global_cycle_count++;
+                break;
+            case STAGE_ID:
+                // add cycle count in func decode_ID
+                mc_ID(&s);
+                push_stage(&s, &stage);
+                break;
+            case STAGE_EX:
+                // alu_result used to pass result to MEM or WB stage
+                // add cycle count in func decode_EX
+                mc_EX(&s, &alu_result);
+                push_stage(&s, &stage);
+                break;
+            case STAGE_MEM:
+                // mem_result used to pass result to WB stage
+                // add cycle count in func decode_MEM
+                mc_MEM(&s, alu_result, &mem_result);
+                push_stage(&s, &stage);
+                break;
+            case STAGE_WB:
+                mc_WB(&s, alu_result, mem_result);
+                push_stage(&s, &stage);
+                break;
+            case STAGE_DONE:
+                printf("INST END\n");
+                goto loop_end;
+        }
+    }
+loop_end:
+    cpu.pc = s.dnpc;
+    // printf("spend %ld cycle\n", global_cycle_count - record);
+}
+
+static inline void show_performance() {
+    printf(ANSI_FMT("Performance: \n\tINST NUM  = %4ld\n\tCYCLE NUM = %4ld\n\tCPI       = %.3f\n", ANSI_FG_YELLOW), ninst, global_cycle_count, (float)global_cycle_count/(float)ninst);
+}
+
+void mc_cpu_exec() {
+    while (running) {
+        mc_exec_once();
+    }
+    show_performance();
+}
+
 void halt_trap(uint64_t pc, uint64_t code){
     if(code){
         printf(ANSI_FMT("HIT BAD TRAP!\n", ANSI_FG_RED));

sim/src/isa_decode.c

@@ -1,6 +1,7 @@
 #include <common.h>
 #include <macro.h>
 #include <pattern.h>
+#include <dbg.h>
 #include <cpu.h>
 #include <memory.h>
 #include <isa_decode.h>
@@ -10,6 +11,7 @@ void decode_operand(Decode *s, int *rd, uint64_t *src1, uint64_t *src2, uint64_t
     int rs1 = BITS(i, 19, 15);
     int rs2 = BITS(i, 24, 20);
     *rd     = BITS(i, 11,  7);
+    s->type = type;
     switch(type) {
         case TYPE_R: src1R(); src2R();         break;
         case TYPE_I: src1R();          immI(); break;

sim/src/main.c

@@ -97,8 +97,14 @@ int run_mc_model(int argc, char *argv[]) {
     char image_file[128] = "";
     sprintf(image_file, "test/build/%s.bin", argv[1]);
     load_image(image_file);
+ 
+    if (argc > 2 && strcmp(argv[2], "--itrace") == 0) {
+        itrace_enabled = 1;
+        init_llvm_disassembler();
+    }
 
-    // TODO: multi_cycle_cpu_exec()
+    init_cpu();
+    mc_cpu_exec();
 
     free(mem);
     return 0;