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feat(debug): import llvm to disasm the instruction
1 parent 568d79c commit 665f6b6

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6 files changed

+85
-114
lines changed

6 files changed

+85
-114
lines changed

‎Dockerfile‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
FROM docker.io/harsonlau/riscv-tools:latest
2+
3+
RUN apt-get update && apt-get install -y llvm-dev
4+
5+
RUN rm -rf /var/lib/apt/lists/*

‎docker-compose.yml‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
version: '3.8'
22
services:
33
dev:
4-
image: docker.io/harsonlau/riscv-tools:latest
4+
build: .
55
volumes:
66
- .:/simulator
77
working_dir: /simulator
8-
command: tail -f /dev/null
8+
command:
9+
tail -f /dev/null

‎sim/Makefile‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
BUILD = build
33
$(shell mkdir -p $(BUILD)/objs)
44

5-
ALL_SRCS = $(wildcard src/*.c)
5+
ALL_SRCS = $(wildcard src/*.c) $(wildcard src/*.cpp)
66
MAIN_SRC = src/main.c
77
TEST_SRCS = src/inst_test.c src/single_test.c
88

@@ -16,11 +16,15 @@ SIMULATOR = $(BUILD)/Simulator
1616
TEST_RUNNER = $(BUILD)/TestRunner
1717

1818
## 2. General Compilation Flags
19+
LLVM_LDFLAGS := $(shell llvm-config --ldflags --libs riscv mc support --system-libs)
20+
1921
CC = gcc
2022
CXX = g++
21-
LD = $(CC)
22-
CFLAGS = -g -I./include -Wall
23-
CXXFLAGS = $(CFLAGS)
23+
LD = $(CXX)
24+
COMMON_FLAGS = -g -I./include -Wall $(shell llvm-config --cppflags)
25+
CFLAGS = $(COMMON_FLAGS) -std=gnu11
26+
CXXFLAGS = $(COMMON_FLAGS) -std=c++17
27+
LDFLAGS = $(LLVM_LDFLAGS)
2428

2529
## 3. Rules
2630
all: $(SIMULATOR)
@@ -35,7 +39,7 @@ $(BUILD)/objs/%.o: src/%.cpp
3539

3640
$(SIMULATOR): $(SIMULATOR_OBJS)
3741
@echo + LD "Simulator" "->" $^
38-
@$(LD) -o $@ $^
42+
@$(LD) $(CXXFLAGS) -o $@ $^ $(LDFLAGS)
3943

4044
$(TEST_RUNNER): $(TEST_RUNNER_OBJS)
4145
@echo + LD "TestRunner" "->" $^

‎sim/src/dbg.c‎

Lines changed: 25 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,21 @@
33
#include <common.h>
44
#include <dbg.h>
55
#include <decode.h>
6+
#include <llvm-c/Disassembler.h>
7+
8+
LLVMDisasmContextRef init_disasm(const char *triple);
9+
void disassemble_inst(LLVMDisasmContextRef disasm_ctx, uint8_t *bytes, int len, uint64_t pc, char *out, size_t out_len);
10+
void cleanup_disasm(LLVMDisasmContextRef disasm_ctx);
11+
12+
static LLVMDisasmContextRef disasm_ctx;
13+
14+
void init_llvm_disassembler() {
15+
disasm_ctx = init_disasm("riscv64-unknown-elf");
16+
}
17+
18+
void cleanup_llvm_disassembler() {
19+
cleanup_disasm(disasm_ctx);
20+
}
621

722
static void cmd_help() {
823
printf("Available commands:\n");
@@ -19,21 +34,23 @@ static void cmd_continue() {
1934
}
2035

2136
static void cmd_quit() {
37+
cleanup_llvm_disassembler();
2238
exit(0);
2339
}
2440

2541
static void cmd_step(int steps) {
42+
char asm_buf[128];
2643
for (int i = 0; i < steps; ++i) {
2744
uint64_t current_pc = cpu.pc;
2845
uint32_t inst_code = mem_read(current_pc, 4);
2946

30-
// Prepare for disassembly
31-
Decode s;
32-
s.pc = current_pc;
33-
s.inst = inst_code;
34-
35-
char asm_buf[128]; // Buffer to hold the disassembled instruction
36-
disassemble(&s, asm_buf);
47+
uint8_t bytes[4];
48+
bytes[0] = inst_code & 0xFF;
49+
bytes[1] = (inst_code >> 8) & 0xFF;
50+
bytes[2] = (inst_code >> 16) & 0xFF;
51+
bytes[3] = (inst_code >> 24) & 0xFF;
52+
53+
disassemble_inst(disasm_ctx, bytes, 4, current_pc, asm_buf, sizeof(asm_buf));
3754

3855
// Print the address and the disassembled instruction
3956
printf("\33[1;34m=> 0x%016lx\33[1;0m: \t%s\n", current_pc, asm_buf);
@@ -72,6 +89,7 @@ static void cmd_examine(int len, uint64_t addr) {
7289
}
7390

7491
void debug_loop() {
92+
init_llvm_disassembler();
7593
char line[256];
7694
while (1) {
7795
printf("(simdb) ");

‎sim/src/decode.c‎

Lines changed: 0 additions & 100 deletions
Original file line numberDiff line numberDiff line change
@@ -165,103 +165,3 @@ const char* riscv_abi_names[32] = {
165165
"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
166166
"s8", "s9", "s10","s11","t3","t4","t5","t6"
167167
};
168-
169-
void disassemble(Decode *s, char *asm_buf) {
170-
int rd = 0;
171-
uint64_t src1 = 0, src2 = 0, imm = 0;
172-
// Extract rs1 and rs2 register indices from the instruction word
173-
int rs1_idx = (s->inst >> 15) & 0x1F;
174-
int rs2_idx = (s->inst >> 20) & 0x1F;
175-
176-
#define INSTPAT_INST(s) ((s)->inst)
177-
#define INSTPAT_MATCH(s, name, type, ... /* sprintf body */ ) { \
178-
decode_operand(s, &rd, &src1, &src2, &imm, concat(TYPE_, type)); \
179-
__VA_ARGS__ ; \
180-
}
181-
182-
INSTPAT_START();
183-
// RV64I
184-
INSTPAT("??????? ????? ????? ??? ????? 01101 11", lui, U, sprintf(asm_buf, "lui %s, 0x%lx", riscv_abi_names[rd], imm));
185-
INSTPAT("??????? ????? ????? ??? ????? 00101 11", auipc, U, sprintf(asm_buf, "auipc %s, 0x%lx", riscv_abi_names[rd], imm));
186-
INSTPAT("??????? ????? ????? ??? ????? 11011 11", jal, J, sprintf(asm_buf, "jal %s, 0x%lx", riscv_abi_names[rd], s->pc + imm));
187-
INSTPAT("??????? ????? ????? 000 ????? 11001 11", jalr, I, sprintf(asm_buf, "jalr %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm));
188-
// BEQ, BNE, BLT, BGE, BLTU, BGEU - printing target address
189-
INSTPAT("??????? ????? ????? 000 ????? 11000 11", beq, B, sprintf(asm_buf, "beq %s, %s, 0x%lx", riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx], s->pc + imm));
190-
INSTPAT("??????? ????? ????? 001 ????? 11000 11", bne, B, sprintf(asm_buf, "bne %s, %s, 0x%lx", riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx], s->pc + imm));
191-
INSTPAT("??????? ????? ????? 100 ????? 11000 11", blt, B, sprintf(asm_buf, "blt %s, %s, 0x%lx", riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx], s->pc + imm));
192-
INSTPAT("??????? ????? ????? 101 ????? 11000 11", bge, B, sprintf(asm_buf, "bge %s, %s, 0x%lx", riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx], s->pc + imm));
193-
INSTPAT("??????? ????? ????? 110 ????? 11000 11", bltu, B, sprintf(asm_buf, "bltu %s, %s, 0x%lx", riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx], s->pc + imm));
194-
INSTPAT("??????? ????? ????? 111 ????? 11000 11", bgeu, B, sprintf(asm_buf, "bgeu %s, %s, 0x%lx", riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx], s->pc + imm));
195-
// LB, LH, LW, LBU, LHU, LWU, LD - in format offset(base)
196-
INSTPAT("??????? ????? ????? 000 ????? 00000 11", lb, I, sprintf(asm_buf, "lb %s, %ld(%s)", riscv_abi_names[rd], imm, riscv_abi_names[rs1_idx]));
197-
INSTPAT("??????? ????? ????? 001 ????? 00000 11", lh, I, sprintf(asm_buf, "lh %s, %ld(%s)", riscv_abi_names[rd], imm, riscv_abi_names[rs1_idx]));
198-
INSTPAT("??????? ????? ????? 010 ????? 00000 11", lw, I, sprintf(asm_buf, "lw %s, %ld(%s)", riscv_abi_names[rd], imm, riscv_abi_names[rs1_idx]));
199-
INSTPAT("??????? ????? ????? 100 ????? 00000 11", lbu, I, sprintf(asm_buf, "lbu %s, %ld(%s)", riscv_abi_names[rd], imm, riscv_abi_names[rs1_idx]));
200-
INSTPAT("??????? ????? ????? 101 ????? 00000 11", lhu, I, sprintf(asm_buf, "lhu %s, %ld(%s)", riscv_abi_names[rd], imm, riscv_abi_names[rs1_idx]));
201-
INSTPAT("??????? ????? ????? 110 ????? 00000 11", lwu, I, sprintf(asm_buf, "lwu %s, %ld(%s)", riscv_abi_names[rd], imm, riscv_abi_names[rs1_idx]));
202-
INSTPAT("??????? ????? ????? 011 ????? 00000 11", ld, I, sprintf(asm_buf, "ld %s, %ld(%s)", riscv_abi_names[rd], imm, riscv_abi_names[rs1_idx]));
203-
// SB, SH, SW, SD - in format offset(base)
204-
INSTPAT("??????? ????? ????? 000 ????? 01000 11", sb, S, sprintf(asm_buf, "sb %s, %ld(%s)", riscv_abi_names[rs2_idx], imm, riscv_abi_names[rs1_idx]));
205-
INSTPAT("??????? ????? ????? 001 ????? 01000 11", sh, S, sprintf(asm_buf, "sh %s, %ld(%s)", riscv_abi_names[rs2_idx], imm, riscv_abi_names[rs1_idx]));
206-
INSTPAT("??????? ????? ????? 010 ????? 01000 11", sw, S, sprintf(asm_buf, "sw %s, %ld(%s)", riscv_abi_names[rs2_idx], imm, riscv_abi_names[rs1_idx]));
207-
INSTPAT("??????? ????? ????? 011 ????? 01000 11", sd, S, sprintf(asm_buf, "sd %s, %ld(%s)", riscv_abi_names[rs2_idx], imm, riscv_abi_names[rs1_idx]));
208-
INSTPAT("??????? ????? ????? 000 ????? 00100 11", addi, I, sprintf(asm_buf, "addi %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm));
209-
// SLTI, SLTIU
210-
INSTPAT("??????? ????? ????? 010 ????? 00100 11", slti, I, sprintf(asm_buf, "slti %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm));
211-
INSTPAT("??????? ????? ????? 011 ????? 00100 11", sltiu, I, sprintf(asm_buf, "sltiu %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm));
212-
// SLLI, SRLI, SRAI, SLLIW, SRLIW, SRAIW
213-
INSTPAT("000000? ????? ????? 001 ????? 00100 11", slli, I, sprintf(asm_buf, "slli %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm & 0x3f));
214-
INSTPAT("000000? ????? ????? 101 ????? 00100 11", srli, I, sprintf(asm_buf, "srli %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm & 0x3f));
215-
INSTPAT("010000? ????? ????? 101 ????? 00100 11", srai, I, sprintf(asm_buf, "srai %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm & 0x3f));
216-
INSTPAT("0000000 ????? ????? 001 ????? 00110 11", slliw, I, sprintf(asm_buf, "slliw %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm & 0x1f));
217-
INSTPAT("0000000 ????? ????? 101 ????? 00110 11", srliw, I, sprintf(asm_buf, "srliw %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm & 0x1f));
218-
INSTPAT("0100000 ????? ????? 101 ????? 00110 11", sraiw, I, sprintf(asm_buf, "sraiw %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm & 0x1f));
219-
// XORI, ORI, ANDI, ADDIW
220-
INSTPAT("??????? ????? ????? 100 ????? 00100 11", xori, I, sprintf(asm_buf, "xori %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm));
221-
INSTPAT("??????? ????? ????? 110 ????? 00100 11", ori, I, sprintf(asm_buf, "ori %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm));
222-
INSTPAT("??????? ????? ????? 111 ????? 00100 11", andi, I, sprintf(asm_buf, "andi %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm));
223-
INSTPAT("??????? ????? ????? 000 ????? 00110 11", addiw, I, sprintf(asm_buf, "addiw %s, %s, %ld", riscv_abi_names[rd], riscv_abi_names[rs1_idx], imm));
224-
// ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
225-
INSTPAT("0000000 ????? ????? 000 ????? 01100 11", add, R, sprintf(asm_buf, "add %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
226-
INSTPAT("0100000 ????? ????? 000 ????? 01100 11", sub, R, sprintf(asm_buf, "sub %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
227-
INSTPAT("0000000 ????? ????? 001 ????? 01100 11", sll, R, sprintf(asm_buf, "sll %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
228-
INSTPAT("0000000 ????? ????? 010 ????? 01100 11", slt, R, sprintf(asm_buf, "slt %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
229-
INSTPAT("0000000 ????? ????? 011 ????? 01100 11", sltu, R, sprintf(asm_buf, "sltu %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
230-
INSTPAT("0000000 ????? ????? 100 ????? 01100 11", xor, R, sprintf(asm_buf, "xor %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
231-
INSTPAT("0000000 ????? ????? 101 ????? 01100 11", srl, R, sprintf(asm_buf, "srl %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
232-
INSTPAT("0100000 ????? ????? 101 ????? 01100 11", sra, R, sprintf(asm_buf, "sra %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
233-
INSTPAT("0000000 ????? ????? 110 ????? 01100 11", or, R, sprintf(asm_buf, "or %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
234-
INSTPAT("0000000 ????? ????? 111 ????? 01100 11", and, R, sprintf(asm_buf, "and %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
235-
// ADDW, SUBW, SLLW, SRLW, SRAW
236-
INSTPAT("0000000 ????? ????? 000 ????? 01110 11", addw, R, sprintf(asm_buf, "addw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
237-
INSTPAT("0100000 ????? ????? 000 ????? 01110 11", subw, R, sprintf(asm_buf, "subw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
238-
INSTPAT("0000000 ????? ????? 001 ????? 01110 11", sllw, R, sprintf(asm_buf, "sllw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
239-
INSTPAT("0000000 ????? ????? 101 ????? 01110 11", srlw, R, sprintf(asm_buf, "srlw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
240-
INSTPAT("0100000 ????? ????? 101 ????? 01110 11", sraw, R, sprintf(asm_buf, "sraw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
241-
// FENCE, FENCE.I, EBREAK, ECALL
242-
INSTPAT("0000??? ????? 00000 000 00000 00011 11", fence, N, sprintf(asm_buf, "fence"));
243-
INSTPAT("0000000 00000 00000 000 00000 00011 11", fencei, N, sprintf(asm_buf, "fence.i"));
244-
INSTPAT("0000000 00001 00000 000 00000 11100 11", ebreak, N, sprintf(asm_buf, "ebreak"));
245-
INSTPAT("0000000 00000 00000 000 00000 11100 11", ecall, N, sprintf(asm_buf, "ecall"));
246-
247-
// RV64M
248-
// MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU
249-
INSTPAT("0000001 ????? ????? 000 ????? 01100 11", mul, R, sprintf(asm_buf, "mul %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
250-
INSTPAT("0000001 ????? ????? 001 ????? 01100 11", mulh, R, sprintf(asm_buf, "mulh %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
251-
INSTPAT("0000001 ????? ????? 010 ????? 01100 11", mulhsu, R, sprintf(asm_buf, "mulhsu %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
252-
INSTPAT("0000001 ????? ????? 011 ????? 01100 11", mulhu, R, sprintf(asm_buf, "mulhu %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
253-
INSTPAT("0000001 ????? ????? 100 ????? 01100 11", div, R, sprintf(asm_buf, "div %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
254-
INSTPAT("0000001 ????? ????? 101 ????? 01100 11", divu, R, sprintf(asm_buf, "divu %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
255-
INSTPAT("0000001 ????? ????? 110 ????? 01100 11", rem, R, sprintf(asm_buf, "rem %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
256-
INSTPAT("0000001 ????? ????? 111 ????? 01100 11", remu, R, sprintf(asm_buf, "remu %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
257-
// MULW, DIVW, DIVUW, REMW, REMUW
258-
INSTPAT("0000001 ????? ????? 000 ????? 01110 11", mulw, R, sprintf(asm_buf, "mulw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
259-
INSTPAT("0000001 ????? ????? 100 ????? 01110 11", divw, R, sprintf(asm_buf, "divw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
260-
INSTPAT("0000001 ????? ????? 101 ????? 01110 11", divuw, R, sprintf(asm_buf, "divuw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
261-
INSTPAT("0000001 ????? ????? 110 ????? 01110 11", remw, R, sprintf(asm_buf, "remw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
262-
INSTPAT("0000001 ????? ????? 111 ????? 01110 11", remuw, R, sprintf(asm_buf, "remuw %s, %s, %s", riscv_abi_names[rd], riscv_abi_names[rs1_idx], riscv_abi_names[rs2_idx]));
263-
264-
// Invalid Opcode
265-
INSTPAT("??????? ????? ????? ??? ????? ????? ??", unk, N, sprintf(asm_buf, "unknown instruction"));
266-
INSTPAT_END();
267-
}

‎sim/src/disasm.c‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
#include <llvm-c/Target.h>
2+
#include <llvm-c/Disassembler.h>
3+
#include <stdio.h>
4+
#include <string.h>
5+
#include <stdlib.h>
6+
7+
LLVMDisasmContextRef init_disasm(const char *triple) {
8+
LLVMInitializeAllTargetInfos();
9+
LLVMInitializeAllTargetMCs();
10+
LLVMInitializeAllDisassemblers();
11+
12+
LLVMDisasmContextRef disasm_ctx = LLVMCreateDisasm(triple, NULL, 0, NULL, NULL);
13+
if (!disasm_ctx) {
14+
fprintf(stderr, "Failed to create LLVM disassembler for triple %s\n", triple);
15+
}
16+
return disasm_ctx;
17+
}
18+
19+
void disassemble_inst(LLVMDisasmContextRef disasm_ctx, uint8_t *instruction_bytes, int num_bytes, uint64_t pc, char *out_buffer, size_t out_buffer_size) {
20+
if (!disasm_ctx) {
21+
snprintf(out_buffer, out_buffer_size, "Disassembler not initialized");
22+
return;
23+
}
24+
25+
size_t bytes_read = LLVMDisasmInstruction(
26+
disasm_ctx,
27+
instruction_bytes,
28+
num_bytes,
29+
pc,
30+
out_buffer,
31+
out_buffer_size
32+
);
33+
34+
if (bytes_read == 0) {
35+
snprintf(out_buffer, out_buffer_size, "unknown instruction");
36+
}
37+
}
38+
39+
void cleanup_disasm(LLVMDisasmContextRef disasm_ctx) {
40+
if (disasm_ctx) {
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LLVMDisasmDispose(disasm_ctx);
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}
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}

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