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Workaround in Zynq port for missing macros when using SDT drivers #1247

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Merged
merged 10 commits into from
May 15, 2025
Merged

Workaround in Zynq port for missing macros when using SDT drivers #1247

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52a2bd9
Modify SetUpSLCRDivisors so that it writes if values are defined
mike919192 Apr 29, 2025
a2ffc6d
Formatting
mike919192 Apr 29, 2025
8c840a9
Formatting
mike919192 Apr 29, 2025
7cec528
Formatting
mike919192 Apr 30, 2025
c376990
Formatting
mike919192 Apr 30, 2025
3bd85b3
Add work around description in README
mike919192 Apr 30, 2025
4797640
Merge branch 'main' into zynq_slcr
mike919192 Apr 30, 2025
22d6eb9
Merge branch 'main' into zynq_slcr
mike919192 May 2, 2025
593de64
Specify that the macros can be defined in FreeRTOSIPConfig.h
mike919192 May 6, 2025
ece83ff
Merge branch 'main' into zynq_slcr
tony-josi-aws May 15, 2025
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8 changes: 8 additions & 0 deletions source/portable/NetworkInterface/Zynq/README.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -40,3 +40,11 @@ It is obligatory to define:

#define ipconfigZERO_COPY_RX_DRIVER 1
#define ipconfigZERO_COPY_TX_DRIVER 1

If using SDT drivers, it may be necessary to define certain link speed divisor values.
This is to work around a driver issue where certain link speeds will not transmit any data
without defining the values.
For example, it may be necessary to define:

#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
81 changes: 44 additions & 37 deletions source/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c
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Original file line number Diff line number Diff line change
Expand Up @@ -500,19 +500,12 @@ unsigned configure_IEEE_phy_speed( XEmacPs * xemacpsp,
return 0;
}

static void SetUpSLCRDivisors( int mac_baseaddr,
int speed )
static void WriteSLCRDivisors( int mac_baseaddr,
u32 SlcrDiv0,
u32 SlcrDiv1 )
{
volatile u32 slcrBaseAddress;

#ifndef PEEP
u32 SlcrDiv0 = 0;
u32 SlcrDiv1 = 0;
u32 SlcrTxClkCntrl;
#endif

*( volatile unsigned int * ) ( SLCR_UNLOCK_ADDR ) = SLCR_UNLOCK_KEY_VALUE;

if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
{
slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
Expand All @@ -522,7 +515,30 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
}

u32 SlcrTxClkCntrl = *( volatile unsigned int * ) ( slcrBaseAddress );
SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
SlcrTxClkCntrl |= ( SlcrDiv1 << 20 );
SlcrTxClkCntrl |= ( SlcrDiv0 << 8 );
*( volatile unsigned int * ) ( slcrBaseAddress ) = SlcrTxClkCntrl;
}

static void SetUpSLCRDivisors( int mac_baseaddr,
int speed )
{
*( volatile unsigned int * ) ( SLCR_UNLOCK_ADDR ) = SLCR_UNLOCK_KEY_VALUE;

#ifdef PEEP
volatile u32 slcrBaseAddress;

if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
{
slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
}
else
{
slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
}

if( speed == 1000 )
{
*( volatile unsigned int * ) ( slcrBaseAddress ) =
Expand All @@ -544,15 +560,17 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
{
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
#endif
}
else
{
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
#endif
}
}
Expand All @@ -561,15 +579,17 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
{
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
#endif
}
else
{
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
#endif
}
}
Expand All @@ -578,37 +598,24 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
if( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
{
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
#endif
}
else
{
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
WriteSLCRDivisors( mac_baseaddr, SlcrDiv0, SlcrDiv1 );
#endif
}
}

/* SDT drivers should not write to the register */
#ifndef SDT
SlcrTxClkCntrl = *( volatile unsigned int * ) ( slcrBaseAddress );
SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
SlcrTxClkCntrl |= ( SlcrDiv1 << 20 );
SlcrTxClkCntrl |= ( SlcrDiv0 << 8 );
*( volatile unsigned int * ) ( slcrBaseAddress ) = SlcrTxClkCntrl;
#else
( void ) SlcrTxClkCntrl;
( void ) SlcrDiv0;
( void ) SlcrDiv1;
( void ) slcrBaseAddress;
#endif
#endif /* ifdef PEEP */
*( volatile unsigned int * ) ( SLCR_LOCK_ADDR ) = SLCR_LOCK_KEY_VALUE;
}


unsigned link_speed;
unsigned Phy_Setup( XEmacPs * xemacpsp )
{
Expand Down