esp32: cache_sram_mmu_set: update the correct register bits

yamt · xiaoxiang781216 · commit a722b74de704 · 2024-08-30T21:46:31.000+08:00
diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c
@@ -199,15 +199,15 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid,
   if (cpu_no == 0)
     {
       regval  = getreg32(DPORT_PRO_CACHE_CTRL1_REG);
-      regval &= ~DPORT_PRO_CMMU_SRAM_PAGE_MODE;
-      regval |= mask_s;
+      regval &= ~DPORT_PRO_CMMU_SRAM_PAGE_MODE_M;
+      regval |= mask_s << DPORT_PRO_CMMU_SRAM_PAGE_MODE_S;
       putreg32(regval, DPORT_PRO_CACHE_CTRL1_REG);
     }
   else
     {
       regval  = getreg32(DPORT_APP_CACHE_CTRL1_REG);
-      regval &= ~DPORT_APP_CMMU_SRAM_PAGE_MODE;
-      regval |= mask_s;
+      regval &= ~DPORT_APP_CMMU_SRAM_PAGE_MODE_M;
+      regval |= mask_s << DPORT_APP_CMMU_SRAM_PAGE_MODE_S;
       putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);
     }
 

Original file line number	Diff line number	Diff line change
`@@ -199,15 +199,15 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid,`
`199`	`199`	`if (cpu_no == 0)`
`200`	`200`	`{`
`201`	`201`	`regval = getreg32(DPORT_PRO_CACHE_CTRL1_REG);`
`202`		`- regval &= ~DPORT_PRO_CMMU_SRAM_PAGE_MODE;`
`203`		`- regval \|= mask_s;`
	`202`	`+ regval &= ~DPORT_PRO_CMMU_SRAM_PAGE_MODE_M;`
	`203`	`+ regval \|= mask_s << DPORT_PRO_CMMU_SRAM_PAGE_MODE_S;`
`204`	`204`	`putreg32(regval, DPORT_PRO_CACHE_CTRL1_REG);`
`205`	`205`	`}`
`206`	`206`	`else`
`207`	`207`	`{`
`208`	`208`	`regval = getreg32(DPORT_APP_CACHE_CTRL1_REG);`
`209`		`- regval &= ~DPORT_APP_CMMU_SRAM_PAGE_MODE;`
`210`		`- regval \|= mask_s;`
	`209`	`+ regval &= ~DPORT_APP_CMMU_SRAM_PAGE_MODE_M;`
	`210`	`+ regval \|= mask_s << DPORT_APP_CMMU_SRAM_PAGE_MODE_S;`
`211`	`211`	`putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);`
`212`	`212`	`}`
`213`	`213`