Documentation/risc-v/esp32[c6]: Add LP_UART support docs

Add LPUART support doc for esp32c6

Signed-off-by: Eren Terzioglu <[email protected]>

Author: eren-terzioglu

Documentation/platforms/risc-v/esp32c6/index.rst

@@ -362,7 +362,7 @@ SPIFLASH         Yes
 SPIRAM           No
 Temp. Sensor     No
 Timers           Yes
-UART             Yes
+UART             Yes     LPUART supported
 USB Serial       Yes
 Watchdog         Yes
 Wi-Fi            Yes

arch/risc-v/src/common/espressif/Make.defs

@@ -178,7 +178,7 @@ endif
 
 ESP_HAL_3RDPARTY_REPO   = esp-hal-3rdparty
 ifndef ESP_HAL_3RDPARTY_VERSION
-	ESP_HAL_3RDPARTY_VERSION = e9a78c811578545e2bc673862d885a15bd6cbf67
+	ESP_HAL_3RDPARTY_VERSION = 98dad3d9b4607df319eca4a7baf50545cda0b1a2
 endif
 
 ifndef ESP_HAL_3RDPARTY_URL

arch/risc-v/src/common/espressif/esp_lowputc.c

@@ -56,6 +56,8 @@
 #  include "soc/uart_pins.h"
 #  include "hal/rtc_io_hal.h"
 #  include "soc/uart_periph.h"
+#  include "driver/rtc_io.h"
+#  include "io_mux.h"
 #endif
 
 /****************************************************************************
@@ -271,19 +273,15 @@ static void esp_lowputc_lp_uart_config_io(const struct esp_uart_s *priv,
   DEBUGASSERT(lp_pin != -1);
 
 #if SOC_LP_IO_CLOCK_IS_INDEPENDENT
-  RTCIO_RCC_ATOMIC()
-    {
-      rtcio_ll_enable_io_clock(true);
-    }
-
+  io_mux_enable_lp_io_clock(lp_pin, true);
 #endif
   rtcio_hal_function_select(lp_pin, RTCIO_LL_FUNC_RTC);
   rtcio_hal_set_direction(pin, direction);
 
   const uart_periph_sig_t *upin =
     &uart_periph_signal[LP_UART_NUM_0].pins[idx];
 #if !SOC_LP_GPIO_MATRIX_SUPPORTED
-  rtcio_hal_iomux_func_sel(lp_pin, upin->iomux_func);
+  rtc_gpio_iomux_func_sel(pin, upin->iomux_func);
 #else
   /* ToDo: Add LP UART for LP GPIO Matrix supported devices (e.g ESP32-P4) */
 #endif /* SOC_LP_GPIO_MATRIX_SUPPORTED */

arch/risc-v/src/esp32c6/hal_esp32c6.mk

@@ -131,6 +131,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)io_mux.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ocode_init.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_init.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_param.c