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1. APB_RAM APB_RAM Public

   APB RAM RTL design with full UVM-based verification using constrained-random testing.

   SystemVerilog

2. SPI_memory_controller_verification SPI_memory_controller_verification Public

   A complete UVM testbench for verifying an SPI memory controller. The environment includes configurable agents, constrained-random and directed sequences for read, write, reset, and error scenarios,…

   SystemVerilog

3. UART_design_verification_UVM UART_design_verification_UVM Public

   UVM-based verification of a configurable UART controller supporting multiple baud rates, data lengths, parity modes, and stop-bit configurations.

   SystemVerilog

4. SV_and_UVM_mini_project SV_and_UVM_mini_project Public

   System verilog and UVM mini projects

   SystemVerilog 1

5. verilog_mini_projects verilog_mini_projects Public

   verilog mini projects implemented on FPGA

   Verilog