This project runs through an FPGA implementation of the Sobel operation for Edge Detection on an image. It is a discrete differential operator that approximates the gradient of an image similar to the Roberts Cross (RC) operator discussed in another repo. Unlike RC, it uses a 3x3 kernel.
"The [Sobel] operator is based on convolving the image with a small, separable, and integer-valued filter in the horizontal and vertical directions and is therefore relatively inexpensive in terms of computations. On the other hand, the gradient approximation that it produces is relatively crude, in particular for high-frequency variations in the image"
Two images, a blackbuck and junkyard boeing plane are used to show the simulation results of a synthesizable rtl Sobel module. QuestaSim is used to simulate the results including a waveform and image outputs.
The goal of this exercise is to visualize the RC Operator in action with a real image using simulation first. It is untested in hardware due to time limitations. Vivado 2023.2 is used for simulation.
This will be quick background of the pipelined Sobel algorithm. The detailed analysis is discussed in the report. Figures in this section are from the report.
Figure 1: 3x3 kernels for both XY direcrions
Figure 2: 3x3 kernels for both XY direcrions
The algorithm is composed of 16 operations in total. Only addition, subtraction and multiply operations are needed. Addition and subtraction are denoted AS and MUL respectively in the figures below. The easiest choice would be to use maximum amount of resources to accomplish the operation. However, this can be lead to increased area and power consumption, which are undesirable. Therefore, the optimal number of resources is engineered through a series of steps for a better design.
Figure 3: The Sequencing Graph (SG) for Sobel. In the report it is Figure 5
With maximum number of resources and multipliers alotting a cycle time of 4 clock cycles (cc) the total latency is 12 cc.
Figure 4: The timing diagram for the Sobel operation. The latency matches in SG of 12 cc
The timing diagram is presented with max resources. Immediately, resource reuse can be visualized which is what is presented in figure below. The details for coming to the 4 AS and 4 MUL are presented in the report. Essentially an architectural configuration graph (ACG) is created where the design space is explored using partial arrangements.
Figure 5: Optimal SG
Although latency does not improve, area and consequenctly power consumption do due to reuse. The timing diagram for the optimal design is presented.
Figure 6: Optimal Timing Diagram using 4 AS and 4 MUL
Once the optimal design is established the data register scheme is implemented as shown below where registers are placed to hold values between clock cycles for a pipelined design.
Figure 7: Data Register Scheme
Next the multiplexer (MUX) tables are designed for state-based operations (not shown here but consult report). The final block diagram of the entire operation is shown below along with the registers and the state buses for the fully pipelined design.
Figure 8: Block Diagram of the optimal design. Colour matched with previous figures related to optimal design
A threshold value is arbitrarily selected and changed in threshold integer in sobelBMP_tb_v2.vhd. Please change that value to your choosing. For best results use grayscale versions of BMP format images of any size. The name of the input and output files should be changed below in string variables inBmp and outBmp, respectively.
constant threshold : integer := 100;
constant inBmp : string := "blackbuck_grayscale.bmp";
constant outbmp : string := "SobelT" & integer'image(threshold) & "_v2_" & inBmp;The placement of input images should be in the Questa folder. The output will be produced and placed in the same folder.
Please load the soble.mpf file located in Questa folder. It will open up the project with 2 files, sobel.vhd and sobelBMP_tb_v2.vhd. In the transcript window, once all the files are loaded, compile all the files. The simulator should automatically determine the compile order and if not compile soble.vhd first. Next execute the DO script by typing
do ../run.do
The run.do file in located parent folder of Questa hence call of .. syntax. If it prompts whether you want to close project select "No". Once the projects compiled and loaded, run,
runtb
for the simulation to begin. In my machine depending on the size, boeing image took about a minute to finish. Please check the output file in Questa folder.
Both the images are of different sizes but the testbench module can handle different sizes dynamically. The original images have been grayscaled for a better RC result. Otherwise the clouds in the boeing result would signficantly interfere in the final image.
Image size is
 Figure 9: Original blackbuck in grayscale |
 Figure 10: Blackbuck with Threshold=64 |
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Figure 9: Original blackbuck in grayscale |
 Figure 10: Blackbuck with Threshold=100 |
Figure 13: The initial portion of timing diagram output with the operations shown for Threshold = 64
Image size is
 Figure 9: Original Boeing in grayscale |
 Figure 10: Boeing with Threshold=64 |
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Figure 9: Original Boeing in grayscale |
 Figure 10: Boeing with Threshold=100 |
Figure 18: The initial portion of timing diagram output with the operations shown for Threshold = 64