tests: Add SMEM PRT test to expose AMD snafu.

tests/d3d12_sparse.c

@@ -328,7 +328,7 @@ static void set_region_size(D3D12_TILE_REGION_SIZE *region, uint32_t num_tiles,
     region->Depth = d;
 }
 
-void test_update_tile_mappings_remap_stress(void)
+static void test_update_tile_mappings_remap_inner(bool smem)
 {
     D3D12_FEATURE_DATA_D3D12_OPTIONS options;
     D3D12_ROOT_SIGNATURE_DESC rs_desc;
@@ -346,6 +346,7 @@ void test_update_tile_mappings_remap_stress(void)
     HRESULT hr;
 
 #include "shaders/sparse/headers/update_tile_mappings.h"
+#include "shaders/sparse/headers/update_tile_mappings_smem.h"
 
     memset(&desc, 0, sizeof(desc));
     desc.no_render_target = true;
@@ -400,7 +401,7 @@ void test_update_tile_mappings_remap_stress(void)
     create_root_signature(context.device, &rs_desc, &context.root_signature);
 
     context.pipeline_state = create_compute_pipeline_state(
-            context.device, context.root_signature, update_tile_mappings_dxbc);
+            context.device, context.root_signature, smem ? update_tile_mappings_smem_dxbc : update_tile_mappings_dxbc);
 
     for (iter = 0; iter < 100; iter++)
     {
@@ -476,7 +477,7 @@ void test_update_tile_mappings_remap_stress(void)
                 ID3D12Resource_GetGPUVirtualAddress(resource) + OFFSET_INTO_PAGE);
         ID3D12GraphicsCommandList_SetComputeRootUnorderedAccessView(context.list, 1,
                 ID3D12Resource_GetGPUVirtualAddress(output_resource));
-        ID3D12GraphicsCommandList_Dispatch(context.list, 1, 1, 1);
+        ID3D12GraphicsCommandList_Dispatch(context.list, smem ? 64 : 1, 1, 1);
         transition_resource_state(context.list, output_resource, D3D12_RESOURCE_STATE_UNORDERED_ACCESS,
                 D3D12_RESOURCE_STATE_COPY_SOURCE);
         get_buffer_readback_with_command_list(output_resource, DXGI_FORMAT_R32_UINT, &rb, context.queue, context.list);
@@ -510,6 +511,16 @@ void test_update_tile_mappings_remap_stress(void)
     destroy_test_context(&context);
 }
 
+void test_update_tile_mappings_remap_vmem(void)
+{
+    test_update_tile_mappings_remap_inner(false);
+}
+
+void test_update_tile_mappings_remap_smem(void)
+{
+    test_update_tile_mappings_remap_inner(true);
+}
+
 void test_update_tile_mappings(void)
 {
     D3D12_TILED_RESOURCE_COORDINATE region_offsets[8];

tests/d3d12_tests.h

@@ -268,7 +268,8 @@ decl_test(test_stencil_export_dxil);
 decl_test(test_raytracing);
 decl_test(test_get_resource_tiling);
 decl_test(test_update_tile_mappings);
-decl_test(test_update_tile_mappings_remap_stress);
+decl_test(test_update_tile_mappings_remap_vmem);
+decl_test(test_update_tile_mappings_remap_smem);
 decl_test(test_sampler_border_color);
 decl_test(test_copy_tiles);
 decl_test(test_buffer_feedback_instructions_sm51);

tests/shaders/sparse/headers/update_tile_mappings_smem.h

@@ -0,0 +1,19 @@
+static const DWORD update_tile_mappings_smem_code_dxbc[] =
+{
+    0x43425844, 0x37ca9b62, 0x19067318, 0xe3db2632, 0x5a979287, 0x00000001, 0x00000108, 0x00000003,
+    0x0000002c, 0x0000003c, 0x0000004c, 0x4e475349, 0x00000008, 0x00000000, 0x00000008, 0x4e47534f,
+    0x00000008, 0x00000000, 0x00000008, 0x58454853, 0x000000b4, 0x00050050, 0x0000002d, 0x0100086a,
+    0x040000a2, 0x00107000, 0x00000000, 0x00000004, 0x0400009e, 0x0011e000, 0x00000000, 0x00000004,
+    0x0200005f, 0x00021012, 0x02000068, 0x00000001, 0x0400009b, 0x00000001, 0x00000001, 0x00000001,
+    0x06000029, 0x00100012, 0x00000000, 0x0002100a, 0x00004001, 0x0000000e, 0x8b0000a7, 0x80002302,
+    0x00199983, 0x00100012, 0x00000000, 0x0010000a, 0x00000000, 0x00004001, 0x00000000, 0x00107006,
+    0x00000000, 0x080000a8, 0x0011e012, 0x00000000, 0x0002100a, 0x00004001, 0x00000000, 0x0010000a,
+    0x00000000, 0x0100003e,
+};
+#ifdef __GNUC__
+#define UNUSED_ARRAY_ATTR __attribute__((unused))
+#else
+#define UNUSED_ARRAY_ATTR
+#endif
+UNUSED_ARRAY_ATTR static const D3D12_SHADER_BYTECODE update_tile_mappings_smem_dxbc = { update_tile_mappings_smem_code_dxbc, sizeof(update_tile_mappings_smem_code_dxbc) };
+#undef UNUSED_ARRAY_ATTR

tests/shaders/sparse/update_tile_mappings_smem.cs_5_0.hlsl

@@ -0,0 +1,8 @@
+StructuredBuffer<uint> tiled_buffer : register(t0);
+RWStructuredBuffer<uint> out_buffer : register(u0);
+
+[numthreads(1, 1, 1)]
+void main(uint3 group_id : SV_GroupID)
+{
+    out_buffer[group_id.x] = tiled_buffer[16384 * group_id.x];
+}