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Releases: IBIResearch/RedPitayaDAQServer

v0.11.2

30 Sep 09:26

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  • Fix bug in the FPGA image. The PDM output for channels 2-4 was always off in the reset manager.
  • Fix communication bugs in the Julia client

v0.11.0

28 Jul 15:06
4525138

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Breaking Changes

  • Breaking: Updated ADC and DAC pipeline requires a new ADC and DAC calibration after the update!
  • Breaking: When not using the ADC calibration the integer values will now be in the range of [-32768, 32767] instead of [-8192, 8191]

Updated ADC Pipeline

  • The decimating pipeline after the ADC now uses the full 16-bit accuracy decreasing the quantization noise which becomes dominant over the ADC noise at high decimations (>256)
  • The FIR filter added in v0.6.0 can now be switched on and off using firEnabled!. For all standard applications the filter should be left on for improved anti-aliasing and flatter frequency response. The filter can be turned off for applications where the delay introduced by the filter is unwanted, e.g. time-based multiplexing

Updated DAC Pipeline

  • increased amplitude resolution of waveform signal components to 16-bit, decreasing the discretization of the sine amplitude from 122 µV to 15 µV
  • increase resolution of DAC pipeline to 16-bit until the final output quantization for improved accuracy when combining different components
  • prevent potential overflow in DAC pipeline when adding multiple components
  • reintroduced signal limiter, which was mistakenly removed in a previous release
  • removed hard limit of 1 V from amplitude components, as the DAC might be able to produce higher amplitudes depending on the calibration

General Updates

  • extended instant reset to ramp down the outputs if ramping is enabled instead of cutting
  • (re)added SCPI interface to enable instant reset
  • added 3-bit counter output with configurable counter speed outputting on DIO2_N (LSB) to DIO4_N (MSB)
  • Improved passing of error messages from SCPI server to the Julia client, SCPI errors still do not throw, but additional info is output as log messages
  • added calibReset!(rp) to reset ADC and DAC calibration to default
  • added serverversion(rp) to query the version of the server running of the RedPitaya
  • improved imgversion to not error on server versions prior to the introduction
  • added two examples on FIR switching
  • deprecated enableRampDown! and enableRampDown due to misleading names and functionality. Use startRampDown!(rp, channel) in the future to start a ramp down. It is not and was never possible to stop a triggered ramp down contrary to what the existence of enableRampDown!(rp, channel, false) might suggest.

Merged Pull Requests

Full Changelog: v0.10.0...v0.11.0

v0.10.0

13 Dec 15:11
addef85

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Add resync of frequency and phases, fix bug in sequence increment and added optional h-bridge DIO output on 7N, 7P

Major changes

Resync #90
H-Bridge #93

v0.8.2

27 Sep 13:17
0b8169c

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Major changes

  • Fix gain error introduced by CIC filter #86

Minor changes

  • scpi-parser was updated to 2.2 #91
  • Updated examples to use CairoMakie instead of PyPlot #92
  • Allow multiple SCPI commands to be handled during data transmission/pipelining

v0.8.0

11 Mar 08:57
e9f9e37

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Major changes

  • scpi-parser was updated to 2.3

Minor changes

  • Setting and reading the DIOs in the wrong mode now issues a warning

v0.7.0

19 Dec 14:51

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Bug fixes in triggering logic:

  • Fix floating external trigger input for master RP
  • Fix client timeout for large samplesPerStep during master trigger off

New calibration option allows limiting of maximum and minimum signal strength as [-1, ..., 1] of output strength

Add version tracking of FPGA image and warnings to client if non-matching versions are detected.

v0.6.0

20 Mar 13:06

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Updated trigger options:

  • Trigger distribution over SATA cable
  • More varied cluster trigger setups
  • Counter-based trigger option

Updated signal generation options:

  • Added arbitrary waveform component to each channel
  • Increased FPGA sequence buffer size and possible step size
  • Increase number of sequence channel to 6: Two analog channel and four pins

Added additional filter to signal acquisition to compensate non-flat amplitude response of decimation filter

v0.5.0

05 Jul 15:07

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Updated signal generation:

  • Signal ramping
  • Improved calibration behaviour
  • Changed sequence to work with signal ramping
  • Removed square waveform (will return in a later release)

Updated client-server communication:

  • Allow for SCPI commands during sample transmission
  • Client offers batch execution for faster configuration
  • Improved communication performance (on Linux)
  • Added return values to SCPI commands

v0.5.0-rc0

04 Jul 09:25
8bec53e

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v0.5.0-rc0 Pre-release
Pre-release

Release candidate for version 0.5.0

v0.4.2

16 Feb 18:53
4014386

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Merge pull request #35 from tknopp/JS/Z7020

Add support for Zynq 7020-based Red Pitayas