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jaenrig-ifx merged 2 commits into from
Jan 12, 2026
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docs/psoc-edge: Added Pins and GPIO docs. #34

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09524a9
docs/psoc-edge: Added Pins and GPIO docs.
jaenrig-ifx Jan 9, 2026
b0954fd
docs/psoc-edge/quickref: Removed harmonized pin.irq() handler variation.
jaenrig-ifx Jan 9, 2026
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10 changes: 6 additions & 4 deletions docs/psoc-edge/general.rst
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.. _psoc_edge_general:

.. include:: links.rst

General information about the PSOC™ Edge port
==============================================

Expand Down Expand Up @@ -44,7 +46,7 @@ Technical specifications
************************
Links for product details:

* `KIT_PSE84_AI product page with relevant documents <https://www.infineon.com/evaluation-board/KIT-PSE84-AI>`_
* `KIT_PSE84_AI MCU Datasheet <TODO: TO BE ADDED>`_


* `KIT_PSE84_AI PSOC™ Edge E84 AI product page <pse84_kit_ai_product_page_>`_
* `KIT_PSE84_AI PSOC™ Edge E84 AI Kit guide <pse84_kit_ai_guide_>`_
* `PSOC™ Edge E8x2, E8x3, E8x5, E8x6 Consumer Datasheet <pse8x_consumer_datasheet_>`_
* `PSOC™ Edge E8x2, E8x3, E8x5, E8x6 Architecture Reference Manual <pse8x_arch_ref_manual_>`_
6 changes: 6 additions & 0 deletions docs/psoc-edge/links.rst
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.. _links.rst:

.. _pse84_kit_ai_product_page: https://www.infineon.com/evaluation-board/KIT-PSE84-AI
.. _pse84_kit_ai_guide: https://www.infineon.com/assets/row/public/documents/30/44/infineon-kit-pse84-ai-user-guide-usermanual-en.pdf
.. _pse8x_consumer_datasheet: https://www.infineon.com/assets/row/public/documents/30/49/infineon-psoc-edge-e8x-consumer-datasheet-datasheet-en.pdf
.. _pse8x_arch_ref_manual: https://www.infineon.com/assets/row/public/documents/30/57/infineon-psoc-edge-e8x-architecture-reference-manual-additionaltechnicalinformation-en.pdf
124 changes: 123 additions & 1 deletion docs/psoc-edge/quickref.rst
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.. _psoc_edge_quickref:

.. include:: links.rst

Quick reference for the PSOC™ Edge
===================================

Expand All @@ -17,4 +19,124 @@ working with this port it may be useful to get an overview of the microcontrolle
:includehidden:

general.rst
installation.rst
installation.rst

Pins and GPIO
-------------

See :ref:`machine.Pin <machine.Pin>` for the complete Pin API reference.
This section focuses on the specific PSOC™ Edge port variations and particularities.

The constructor
^^^^^^^^^^^^^^^

The controller pin naming follows the nomenclature ``P<port>_<pin>``, where:

- ``<port>`` is a numeric identifier for the port (e.g., 0-21 for the PSOC™ Edge E84)
- ``<pin>`` is the pin number within that port.

Use the respective board pinout diagram to find the available pins and their locations.

This is the ``id`` that needs to be passed to the constructor in one of the following formats:

- As a **string label**, single or double quoted: ``'P<port>_<pin>'`` or ``"P<port>_<pin>"``
- A **pre-instantiated object** ``Pin.cpu.<pin>`` or ``Pin.board.<pin>``.

::

from machine import Pin

p_in = Pin('P0_0', Pin.IN)
p_out = Pin("P7_0", Pin.OUT, value=False)

p = Pin(Pin.cpu.P17_1, Pin.OPEN_DRAIN)


The pre-instantiated object can be used directly without calling the constructor.
Instead, you can use ``init()`` to configure it.

::

from machine import Pin

pin = Pin.cpu.P17_0
pin.init(mode=Pin.IN)


.. tip::
Use the REPL interface to discover the available user pins, using tab for completion:

>>> from machine import Pin
>>> Pin.cpu.P
P10_5 P10_7 P11_3 P12_3
P13_0 P13_1 P13_2 P13_3
P13_4 P13_5 P13_6 P13_7
P14_0 P14_1 P14_2 P14_3
P14_4 P14_5 P14_6 P14_7
P15_0 P15_1 P15_2 P15_3
P15_4 P15_5 P15_6 P15_7
P16_0 P16_1 P16_2 P16_3
P16_4 P16_5 P16_6 P16_7
P17_0 P17_1 P17_2 P17_3
P17_4 P17_5 P17_7 P20_3
P20_4 P20_5 P20_6 P20_7
P21_1 P21_2 P21_3 P21_4
P21_5 P21_6 P21_7 P3_0
P3_1 P6_4 P6_6 P7_0
P7_7 P8_0 P8_1 P8_5
P8_6 P9_0 P9_1 P9_2
P9_3

.. Add Pin.board.xxx when we define some pins. This will be more helpful.

.. warning::
Currently no ``Pin.board.<pin>`` are defined for the PSOC™ Edge E84 AI Kit.

In addition to the supported ``pull`` configuration values, ``PULL_UP_DOWN`` is also available in this port.

The ``drive`` parameter accepts up to 8 levels, which set the following drive strength for the pin:

- ``DRIVE_0``: 1mA/2mA drive current (normal/high speed IO)
- ``DRIVE_1``: 2mA/4mA drive current (normal/high speed IO)
- ``DRIVE_2``: 3mA/6mA drive current (normal/high speed IO)
- ``DRIVE_3``: 4mA/8mA drive current (normal/high speed IO)
- ``DRIVE_4``: 5mA/10mA drive current (normal/high speed IO)
- ``DRIVE_5``: 6mA/12mA drive current (normal/high speed IO)
- ``DRIVE_6``: 7mA/14mA drive current (normal/high speed IO)
- ``DRIVE_7``: 8mA/16mA drive current (normal/high speed IO)

For more information about drive strength, check the PSOC™ Edge `Datasheet <pse8x_consumer_datasheet_>`_ and `Architecture Reference Manual <pse8x_arch_ref_manual_>`_.

.. note::

The following constructor arguments and/or configuration values are NOT supported in this port:

- ``alt``: Alternate functionality is not supported.
- ``mode``: ``Pin.ALT``, ``Pin.ALT_OPEN_DRAIN``, and ``Pin.ANALOG`` modes are not supported.

Methods
^^^^^^^

.. method:: Pin.irq(handler=None, trigger=(Pin.IRQ_FALLING | Pin.IRQ_RISING), priority=7)

The following parameters have port-specific behavior:

- ``priority``: Priority values range from 7 (lowest) to 0 (highest). Default is 7.

.. note::

All pins on the same port share the same interrupt line. Therefore, only one priority can be set for all pins on the same port.
If multiple pins configure interrupts for the same port, the highest priority will be used.
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@NikhitaR-IFX NikhitaR-IFX Jan 12, 2026

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Mm how does it work then if you have 2 pins in same port with interrupt configuration? How do you know which gets executed first?

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@jaenrig-ifx jaenrig-ifx Jan 12, 2026

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The interrupt executed first will be the first taking place (first come first served) when it comes to the same port pins. As they have both the same priority level, none should be pausing the other to take precedence.
Or you mean how do we know which interrupt is triggering the callback?

If only one pin is configured for an interrupt, its priority can be reconfigured to any value.

.. note::

The following ``irq()`` features are not supported in this port:

- ``trigger``: The ``Pin.IRQ_LOW_LEVEL`` and ``Pin.IRQ_HIGH_LEVEL`` triggers are not supported.
- ``wake``: The wake parameter is currently not supported.
- ``hard``: This parameter is ignored. It can be passed but currently has no effect.

.. note::

**None** of the non-core methods from the Pin API are currently implemented for this port.
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