Gate materialization tests by capability

[voltjia]

Summary

• Add isolated, cached subprocess probes for CUDA, Triton AOT, and TileLang materialization.
• Skip optional tests only after a probe reports an unavailable capability; malformed output, timeouts, and unexpected probe failures remain errors.
• Gate the exact AOT, reload, and auto-tuning parameters while keeping mandatory compiler coverage unmarked.

The probes compile and reload real artifacts without importing NineToothed, so a supported result cannot hide a later project regression. TileLang was installed or verified before the accelerator runs.

pytest output:

Local protocol/classification subset:
...........................                                              [100%]
27 passed, 4 deselected

NVIDIA (accelerator-dev/nvidia:latest, exact head 6773cfec):
.....................................................                    [100%]
53 passed in 34.60s

Iluvatar (image e8382905ffaa, exact head 6773cfec):
...............................sssssssssss.ssssssssss                    [100%]
32 passed, 21 skipped in 5.38s

Hygon (sglang-deepseek-v4-dev-zkjh, exact head 6773cfec):
...............................sssssssssss.ssssssssss                    [100%]
32 passed, 21 skipped in 35.11s

The Hygon image already provides TileLang 0.1.9. Its unrelated sglang/vLLM
package conflicts are recorded separately from the scoped test result.