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ConchuODLorenzo Pieralisi
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dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties
Recent versions of dt-schema warn about unevaluatedProperties: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml The clocks are required to enable interfaces between the FPGA fabric and the core complex, so add them to the binding. Link: https://lore.kernel.org/r/[email protected] Fixes: 6ee6c89 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") Signed-off-by: Conor Dooley <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
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Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml

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@@ -25,6 +25,33 @@ properties:
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- const: cfg
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- const: apb
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clocks:
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description:
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Fabric Interface Controllers, FICs, are the interface between the FPGA
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fabric and the core complex on PolarFire SoC. The FICs require two clocks,
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one from each side of the interface. The "FIC clocks" described by this
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property are on the core complex side & communication through a FIC is not
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possible unless it's corresponding clock is enabled. A clock must be
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enabled for each of the interfaces the root port is connected through.
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This could in theory be all 4 interfaces, one interface or any combination
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in between.
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minItems: 1
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items:
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- description: FIC0's clock
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- description: FIC1's clock
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- description: FIC2's clock
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- description: FIC3's clock
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clock-names:
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description:
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As any FIC connection combination is possible, the names should match the
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order in the clocks property and take the form "ficN" where N is a number
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0-3
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minItems: 1
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maxItems: 4
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items:
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pattern: '^fic[0-3]$'
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interrupts:
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minItems: 1
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items:

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