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Merge tag 'imx-fixes-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.19, round 2: - Fix the SDIO description for imx7d-smegw01 board to ensure there is no communication made at 1.8V. - Fix pgc_ispdwp power-domain clock, which should be IMX8MP_CLK_MEDIA_ISP_ROOT. - Re-enable framebuffer support in mxs_defconfig to fix a Kconfig regression. - A series from Peng Fan (and Sherry Sun) fixing various pads on i.MX8MP based boards to leave reserved bits untouched. * tag 'imx-fixes-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8mp-icore-mx8mp-edim2.2: correct pad settings arm64: dts: imx8mp-phyboard-pollux-rdk: correct i2c2 & mmc settings arm64: dts: imx8mp-phyboard-pollux-rdk: correct eqos pad settings arm64: dts: imx8mp-phyboard-pollux-rdk: correct uart pad settings arm64: dts: imx8mp-venice-gw74xx: correct pad settings arm64: dts: imx8mp-evk: correct I2C3 pad settings arm64: dts: imx8mp-evk: correct I2C1 pad settings arm64: dts: imx8mp-evk: correct I2C5 pad settings arm64: dts: imx8mp-evk: correct vbus pad settings arm64: dts: imx8mp-evk: correct eqos pad settings arm64: dts: imx8mp-evk: correct vbus pad settings arm64: dts: imx8mp-evk: correct gpio-led pad settings arm64: dts: imx8mp-evk: correct the uart2 pinctl value arm64: dts: imx8mp-evk: correct mmc pad settings ARM: mxs_defconfig: Enable the framebuffer arm64: dts: imx8mp: correct clock of pgc_ispdwp ARM: dts: imx7d-smegw01: Fix the SDIO description Link: https://lore.kernel.org/r/20220629021244.GL819983@dragon Signed-off-by: Arnd Bergmann <[email protected]>
2 parents a38dbb4 + 8630354 commit 1f66f63

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7 files changed

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7 files changed

+149
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lines changed

‎arch/arm/boot/dts/imx7d-smegw01.dts

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -216,10 +216,8 @@
216216
pinctrl-names = "default";
217217
pinctrl-0 = <&pinctrl_usdhc2>;
218218
bus-width = <4>;
219+
no-1-8-v;
219220
non-removable;
220-
cap-sd-highspeed;
221-
sd-uhs-ddr50;
222-
mmc-ddr-1_8v;
223221
vmmc-supply = <&reg_wifi>;
224222
enable-sdio-wakeup;
225223
status = "okay";

‎arch/arm/configs/mxs_defconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
9393
CONFIG_DRM=y
9494
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
9595
CONFIG_DRM_MXSFB=y
96+
CONFIG_FB=y
9697
CONFIG_FB_MODE_HELPERS=y
9798
CONFIG_LCD_CLASS_DEVICE=y
9899
CONFIG_BACKLIGHT_CLASS_DEVICE=y

‎arch/arm64/boot/dts/freescale/imx8mp-evk.dts

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -395,41 +395,41 @@
395395
&iomuxc {
396396
pinctrl_eqos: eqosgrp {
397397
fsl,pins = <
398-
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
399-
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
400-
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
401-
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
402-
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
403-
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
404-
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
405-
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
406-
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
407-
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
408-
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
409-
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
410-
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
411-
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
412-
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
398+
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
399+
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
400+
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
401+
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
402+
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
403+
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
404+
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
405+
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
406+
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
407+
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
408+
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
409+
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
410+
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
411+
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
412+
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
413413
>;
414414
};
415415

416416
pinctrl_fec: fecgrp {
417417
fsl,pins = <
418-
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
419-
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
420-
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
421-
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
422-
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
423-
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
424-
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
425-
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
426-
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
427-
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
428-
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
429-
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
430-
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
431-
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
432-
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
418+
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
419+
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
420+
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
421+
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
422+
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
423+
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
424+
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
425+
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
426+
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
427+
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
428+
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
429+
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
430+
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
431+
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
432+
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
433433
>;
434434
};
435435

@@ -461,28 +461,28 @@
461461

462462
pinctrl_gpio_led: gpioledgrp {
463463
fsl,pins = <
464-
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
464+
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
465465
>;
466466
};
467467

468468
pinctrl_i2c1: i2c1grp {
469469
fsl,pins = <
470-
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
471-
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
470+
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
471+
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
472472
>;
473473
};
474474

475475
pinctrl_i2c3: i2c3grp {
476476
fsl,pins = <
477-
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
478-
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
477+
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
478+
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
479479
>;
480480
};
481481

482482
pinctrl_i2c5: i2c5grp {
483483
fsl,pins = <
484-
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
485-
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
484+
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
485+
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
486486
>;
487487
};
488488

@@ -500,20 +500,20 @@
500500

501501
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
502502
fsl,pins = <
503-
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
503+
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
504504
>;
505505
};
506506

507507
pinctrl_uart2: uart2grp {
508508
fsl,pins = <
509-
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
510-
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
509+
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
510+
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
511511
>;
512512
};
513513

514514
pinctrl_usb1_vbus: usb1grp {
515515
fsl,pins = <
516-
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19
516+
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
517517
>;
518518
};
519519

@@ -525,7 +525,7 @@
525525
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
526526
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
527527
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
528-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
528+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
529529
>;
530530
};
531531

@@ -537,7 +537,7 @@
537537
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
538538
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
539539
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
540-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
540+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
541541
>;
542542
};
543543

@@ -549,7 +549,7 @@
549549
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
550550
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
551551
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
552-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
552+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
553553
>;
554554
};
555555

‎arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -110,28 +110,28 @@
110110
&iomuxc {
111111
pinctrl_eqos: eqosgrp {
112112
fsl,pins = <
113-
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
114-
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
115-
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
116-
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
117-
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
118-
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
119-
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
120-
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
121-
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
122-
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
123-
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
124-
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
125-
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
126-
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
127-
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x19
113+
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
114+
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
115+
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
116+
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
117+
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
118+
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
119+
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
120+
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
121+
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
122+
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
123+
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
124+
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
125+
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
126+
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
127+
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10
128128
>;
129129
};
130130

131131
pinctrl_uart2: uart2grp {
132132
fsl,pins = <
133-
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
134-
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
133+
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
134+
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
135135
>;
136136
};
137137

@@ -151,7 +151,7 @@
151151
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
152152
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
153153
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
154-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
154+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
155155
>;
156156
};
157157

@@ -163,13 +163,13 @@
163163

164164
pinctrl_reg_usb1: regusb1grp {
165165
fsl,pins = <
166-
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
166+
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10
167167
>;
168168
};
169169

170170
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
171171
fsl,pins = <
172-
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
172+
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
173173
>;
174174
};
175175
};

‎arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -116,48 +116,48 @@
116116
&iomuxc {
117117
pinctrl_eqos: eqosgrp {
118118
fsl,pins = <
119-
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
120-
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
121-
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
122-
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
123-
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
124-
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
125-
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
126-
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
127-
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
128-
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
129-
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
130-
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
131-
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
132-
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
119+
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
120+
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
121+
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
122+
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
123+
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
124+
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
125+
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
126+
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
127+
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
128+
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
129+
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
130+
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
131+
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
132+
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
133133
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
134134
>;
135135
};
136136

137137
pinctrl_i2c2: i2c2grp {
138138
fsl,pins = <
139-
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
140-
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
139+
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
140+
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
141141
>;
142142
};
143143

144144
pinctrl_i2c2_gpio: i2c2gpiogrp {
145145
fsl,pins = <
146-
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
147-
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
146+
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
147+
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
148148
>;
149149
};
150150

151151
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
152152
fsl,pins = <
153-
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
153+
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
154154
>;
155155
};
156156

157157
pinctrl_uart1: uart1grp {
158158
fsl,pins = <
159-
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
160-
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
159+
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
160+
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
161161
>;
162162
};
163163

@@ -175,7 +175,7 @@
175175
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
176176
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
177177
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
178-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
178+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
179179
>;
180180
};
181181

@@ -187,7 +187,7 @@
187187
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
188188
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
189189
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
190-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
190+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
191191
>;
192192
};
193193

@@ -199,7 +199,7 @@
199199
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
200200
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
201201
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
202-
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
202+
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
203203
>;
204204
};
205205
};

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