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Arty Board Examples
Julian Kemmerer edited this page Nov 4, 2020
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These examples have been crafted for the Digilent Arty Artix-35T board. If you want support for another board or have any questions at all feel free to reach out and ask!
- Clone the PipelineC git repo which includes the Arty example files.
- Follow the running the PipelineC tool steps to generate VHDL.
- Uncomment ports from
examples/arty/Arty-A7-35-Master.xdcand add/connect port wires as needed inexamples/arty/board.vhd. - Run Vivado as normal (click Generate Bitstream).
The source for this example can be found here. Please see a full break down of the blinking leds example here.
The source for this example can be found here. A full break down of PipelineC results can be found here.
An example storing UART messages in DDR memory and then reading those messages back - DDR loopback. Includes test driver C code as well.
A UDP packet loopback example is here. Is is kinda old at this point but willing to revive it! It uses a free trial, ultimately paid, Xilinx TEMAC core - would like to get rid of that.