Example: StreamSoC

WORK IN PROGRESS

---

This page describes a RISCV SoC that extends the FFT SoC design TODO link

add links from FFT soc page (and riscv page), and camera page to new StreamSoC page top of writeup is hardware image with pmods and dev boards and monitor

Intro

Goal started with doing RTL design easier, and RTL design rarely sits alone without a companion CPU anymore who what when where why RISCV CPU with custom dataflow accelerator hardware all created with PipelineC with demo of audio and video stream processing

add empty stream soc diagram

StreamSoc

RISCV cpu and network of dataflow elements mean to process streaming data basic cpu summary, stages, memory map CSRs, shared resource bus DDR3, point to fft soc

PipelineC

pipelines, state machines, clock domain crossings, system buses AXI etc,

Software Prototype

Direct stream of data into memory (typically shared DDR3, could be local BRAM too) Proove out algorithm slowly in Desktop software, then into embedded CPU, then can incrementally move parts into hardware all c

Hardware Dataflow

take advantage of FPGA for what intended, low latnecy high throughput data streams PipelineC autopipeling extendable across dev boards

Applications

FFT Visualizer and Video Feedback Experiment

DO WRITEUP FOR VIDEO PIPELINE work alone Example: Video Pipeline add full currently stream soc diagram is FFT SoC plus camera input added to dataflow with ice40 dev board too all pipelinec

This is hobby, fun audio visualizer and trying for video feedback visuals love comp arch, want to help other people achieve their designs, learn new algorithms and hardware realizations

Other Applications

Mention wireguard project crypto dataflow

Future work

best way to scale to large programmable dataflow network to large flexible networks is via on chip network (NoC)