Example: Camera
WORK IN PROGRESS
This page describes getting a video stream input into an FPGA development board via a Camera PMOD.
This example is from a series of examples designed for dev boards.
TODO link to code.
The camera used in this demo is the Omnivision OV2640.
Using the camera is documented in hardware application notes and consists of:
- Clocks + Reset:
- Hold the camera in reset
- Provide clock to camera for it's PLL
- Take the camera out of reset
- Configure the camera over I2C like Serial Camera Control Bus (SCCB)
- Receive video stream over Digital Video Port (DVP)
On the Arty dev board PMOD connectors C and D are used. Arty PMOD C = Camera PMOD J2, Arty PMOD D = Camera PMOD J3.
TODO ALL PINS little table? or just link
XK system clock This corresponds output signal Arty PMOD C, row B, I/0 2 aka .xdc top level pin jc(5).
The XVCLK System clock input pin is the primary clock input for the camera. The camera datasheet and online examples use a typical rate of 24MHz. On the camera PMOD J2 connector, the system clock input pin labeled XK.
The hardware application notes show holding in reset (active low) for at least 3ms. Then SCCB initialization should occur at least 3ms after that.
A write transaction requires three 'phases' of 8b values:
-
ID Address, device id, to select a specific device -
Sub-address, register address, to select specific register -
Write Data, the data to be written to the selected device's register
A read transaction occurs over two two-phase transmission cycles (wtf?):
-
ID Address, device id, to select a specific device -
Sub-address, register address, to select specific register
Then again the ID (wtf?):
-
ID Address, device id, to select a specific device
Then camera drives the bus during final phase:
-
Read Data, the data read from the selected device's register
These 8b value 'phases' are padded with a 9th control/status bit called the Don't-Care bit (sigh, wtf?).
Ex. manufacturer id