Example: Camera

WORK IN PROGRESS

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This page describes getting a video stream input into an FPGA development board via a Camera PMOD.

This example is from a series of examples designed for dev boards.

TODO link to code.

Camera Module

The camera used in this demo is the Omnivision OV2640.

Using the camera is documented in hardware application notes and consists of:

• Clocks + Reset:
  • Hold the camera in reset
  • Provide clock to camera for it's PLL
  • Take the camera out of reset
• Configure the camera over I2C like Serial Camera Control Bus (SCCB)
• Receive video stream over Digital Video Port (DVP)

Pinout

On the Arty dev board PMOD connectors C and D are used. Arty PMOD C = Camera PMOD J2, Arty PMOD D = Camera PMOD J3.

TODO ALL PINS little table? or just link XK system clock This corresponds output signal Arty PMOD C, row B, I/0 2 aka .xdc top level pin jc(5).

Clocks

The XVCLK System clock input pin is the primary clock input for the camera. The camera datasheet and online examples use a typical rate of 24MHz. On the camera PMOD J2 connector, the system clock input pin labeled XK.

Reset

The hardware application notes show holding in reset (active low) for at least 3ms. Then SCCB initialization should occur at least 3ms after that.

The PMOD used in this design does not expose the camera reset signal. The camera comes out of reset at power on and will be initialized after the above specified initialization delay.

Serial Camera Control Bus (SCCB)

Per the SCCB spec: Reads from the camera, and writes to the camera are completed by transferring bytes. Each 8b value is a 'phase'. Phases are padded with a 9th control/status bit called the Don't-Care bit (sigh, wtf?).

Like I2C, serial data is to be sampled during (at the middle of) clock=1 time, data changes during (at the middle of) clock=0 time.

The typical clock cycle time from SCCB spec is 10us, or 100Khz.

Idle, Start, Stop

• Idle:
  • Clock: 1,high
  • Data: tri-state, floating, high-z

Details from the SCCB spec section 1.1 2-Wire SCCB Interface along with some example projects seem to not rely on being able to maintain the data line in a tri-state mode. And thus also include using high to-or-from low transitions as part of signalling start and end of transmission:

• Start:
  • Clock: high to low
    • First MSB data bit changes at mid point of clock low time
  • Data: 1 to 0 during clock high time
    • Driving of first MSB data bit occurs after 0 time
• Stop:
  • Clock: low to high
  • Data: 0 to 1 during clock high time
    • mid point of last clock low time is when driving 0 time starts

Read

A read transaction occurs over two two-phase transmission cycles:

Transfer 1: two phase write to specify device and register

• ID Address: 7b device id, to select a specific device, and 1b write=0 flag.
• Sub-address: 8b register address, to select specific register

Transfer 2: two phase read, to specify read from device and receive data

• ID Address: 7b device id, to select a specific device, and 1b read=1 flag.
• Read Data: 8b data read from the selected device's register
  • Camera drives the bus during this phase

For example: reading the camera's manufacturer id register looks like:

• ID=0x60 to select the OV2640 camera
• Address=0x0A to select the PIDH product ID number MSBs, expected read data value of PIDH=0x26

Write

A write transaction requires three phases of values:

• ID Address: 7b device id, to select a specific device, and 1b write=0 flag.
• Sub-address, 8b register address, to select specific register
• Write Data, 8b data to be written to the selected device's register

Video Stream

Video stream consists of these signals all sync to the pixel clock:

• Pixel Clock
• VSYNC
• HREF
• 8bit data