Example: Camera
WORK IN PROGRESS
This page describes getting a video stream input into an FPGA development board via a Camera PMOD.
This example is from a series of examples designed for dev boards.
The camera used in this demo is the Omnivision OV2640.
Using the camera consists of:
- Clocks + Reset:
- Hold the camera in reset
- Provide clock to camera for it's PLL
- Take the camera out of reset
- Configure the camera over I2C like Serial Camera Control Bus (SCCB)
- Receive video stream over Digital Video Port (DVP)
On the Arty dev board PMOD connectors C and D are used. Arty PMOD C = Camera PMOD J2, Arty PMOD D = Camera PMOD J3.
The XVCLK System clock input pin is the primary clock input for the camera. The camera datasheet and online examples use a typical rate of 24MHz. On the camera PMOD J2 connector, the system clock input pin labeled XK, it is the second data pin of the outer/bottom row of pins (6th data pin overall). This corresponds output signal Arty PMOD C, row B, I/0 2 aka .xdc top level pin jc(5).
Ex. manufacturer id