Example: Ethernet

This is a break down of an Arty board based example that receives Ethernet frames, does some work on the payload, and sends a response frame back.

This example is from a series of examples designed for the Arty Board. See that page for basic instruction for using the Arty board.

Source

The source code for this project can be primarily found in work_app.c. This project uses the Xilinx TEMAC core at this for easy access to the off chip Ethernet PHY. work_app.c describes three main functions / clock domains: rx_main() which is connected the receive part of the TEMAC core, tx_main() which is connected to the transmit part of the TEMAC core, and work_pipeline() which has the work() function to be done.

In both the RX and TX functions two things occur: 1) The 8b AXIS to/from the TEMAC is converted to 32b AXIS. This is done using 'raw VHDL' code as to easily make use of existing AXIS data width converter IP freely available from Xilinx. 2) The 32b AXIS from the TEMAC is parsed to pull out Ethernet header info, ex. mac addresses, see eth_32.c.

Bytes from Ethernet are (de)serialized, converted to user struct types, buffered in FIFOs inputs_fifo and outputs_fifo, and sent to/from the work_pipeline() function.

// This pipeline does the following:
//    Reads work inputs from rx fifo
//    Does work on the work inputs to form the work outputs
//    Writes outputs into tx fifo
#pragma MAIN_MHZ work_pipeline 150.0   // Actually running at 100MHz but need margin since near max utilization
void work_pipeline()
{
  // Read incoming work inputs from rx_main
  inputs_fifo_read_t input_read = inputs_fifo_READ_1(1); 
  work_inputs_t inputs = input_read.data[0]; 
  
  // Do work on inputs, get outputs
  work_outputs_t outputs = work(inputs);

  // Write outgoing work outputs into tx_main
  work_outputs_t output_wr_data[1];
  output_wr_data[0] = outputs;
  outputs_fifo_write_t output_write = outputs_fifo_WRITE_1(output_wr_data, input_read.valid);
  // TODO overflow wire+separate state
}

PipelineC Tool Output

Pipeline Map

The compiler produces a text representation of what operations occur at which point during the pipeline (i.e. how long each operation takes and when). Inputs flow from top to bottom. Functions listed on the same lines are occurring in parallel.

TODO PIPELINE MAP

Throughput Sweep

TODO TOOL RESULTS

Vivado Results

Resource usage:

TODO IMAGE

C Driver/Test Code

TODO

Ethernet Loopback Example