Vitis

WORK IN PROGRESS

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This page describes the current state of PipelineC+Xilinx Vitis integration. It primarily consists of a demo showing a PipelineC pipeline in a Vitis AXIS based design.

Beginning in PR 127, the primary person behind this fantastic work is @bartokon. If you have any Vitis-related questions or comments they are likely the best person to contact.

The files discussed here are in the PipelineC repo at examples/vitis_import.

Files

• axis.c: PipelineC main file
  • Pipeline the_pipeline()
    • Function is autopipelined to meet MAIN_MHZ specified
    • Has input and output wires connected to the IO and Control logic
  • IO and Control io_and_ctrl()
    • Has wires to and from the pipeline
    • Inputs go directly into pipeline
    • After being output from the pipeline, output data is stored in FIFO
    • Output data FIFO is used to read data out as out_ready is signaled
    • FIFO is required because auto-pipelined functions cannot be directly connected to feedback/ready signals yet
• build.sh: script to run pipelinec tool and produce VHDL
• vitis_scripts: All Vitis files
  • build_all.sh: Run all builds for specified TARGET
    • Vivado: package_xo.tcl
    • Vitis: vitis_compile.sh and vitis_link.sh
    • gpp.sh C++ compile
    • Runs tests: test.sh
  • includes directory:
    • Xilinx Core Library xcl2.cpp and xcl2.hpp
  • sources directory:
    • xrt.ini Xilinx Runtime Config
    • Vitis Config: vitis_hls.cfg and vitis_link.cfg
    • package_xo.tcl script used by Vivado to package VHDL files with an AXIS interface into an IP .XO file
      • utils.tcl has helpers for configuring clocks and AXIS signals
    • main.cpp:
      • Based on Vitis Hello World demo and Stream Kernel Integration Tutorial
      • Host CPU program
      • Hardware Emulation (Simulation):
        • Xilinx runtime config xrt.ini file configures running Vivado xsim simulation.
      • Hardware Test (Alveo board):
        • Programs the programmable logic (target hardware is Alveo in this example).
        • Creates IO buffers in the HBM memory.
        • Runs the hardware kernel that sends and receives streams to-from the FPGA.
      • Data received from FPGA is stored and checked against expected results.
      • Uses helper conversions of streaming data to and from AXI bus access: maxi_to_stream.cpp and stream_to_maxi.cpp

Build

Tested with Vivado/Vitis tools version 2022.2

Scripts are used to generate Vitis HLS IPs that transfer data to/from PipelineC generated IP.

Streaming interfaces are used as communication channel.

PipelineC IP is packaged as an .XO and connected with Vitis at linking stage.

• Source Xilinx env first
  • for example: source /tools/Xilinx/Vitis/2022.2/settings64.sh
• Use build_all.sh to build and run example project.
  • If you wish to build for hw change TARGET in build_all.sh script.

Hardware Emulation (Simulation)

Setting TARGET=hw_emu in the Makefile will cause test.sh to run main.cpp configured to do the following:

• Reads xrt.ini file that specifies that hw_emu should be run with xsim and gui
• Can monitor debug ports
• Data received from simulation is stored and checked against expected results.

Hardware Test

Tested on Alveo hardware.

Setting TARGET=hw in the Makefile will cause test.sh to run main.cpp configured to do the following:

• Programs the programmable logic
• Creates IO buffers in the HBM memory.
• Runs the hardware kernel that sends and receives streams to-from the FPGA.
• Data received is stored and checked against expected results.