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Merged
MrSidims merged 1 commit into from
Oct 21, 2025
Merged

[NFC] Update gather/scatter translation after 573ca36 #3406

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12 changes: 5 additions & 7 deletions lib/SPIRV/SPIRVWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5047,10 +5047,9 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
}
SPIRVType *Ty = transScavengedType(II);
auto *PtrVector = transValue(II->getArgOperand(0), BB);
uint32_t Alignment =
cast<ConstantInt>(II->getArgOperand(1))->getZExtValue();
auto *Mask = transValue(II->getArgOperand(2), BB);
auto *FillEmpty = transValue(II->getArgOperand(3), BB);
uint32_t Alignment = II->getParamAlign(0).valueOrOne().value();
auto *Mask = transValue(II->getArgOperand(1), BB);
auto *FillEmpty = transValue(II->getArgOperand(2), BB);
std::vector<SPIRVWord> Ops = {PtrVector->getId(), Alignment, Mask->getId(),
FillEmpty->getId()};
return BM->addInstTemplate(internal::OpMaskedGatherINTEL, Ops, BB, Ty);
Expand All @@ -5067,9 +5066,8 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
}
auto *InputVector = transValue(II->getArgOperand(0), BB);
auto *PtrVector = transValue(II->getArgOperand(1), BB);
uint32_t Alignment =
cast<ConstantInt>(II->getArgOperand(2))->getZExtValue();
auto *Mask = transValue(II->getArgOperand(3), BB);
uint32_t Alignment = II->getParamAlign(1).valueOrOne().value();
auto *Mask = transValue(II->getArgOperand(2), BB);
std::vector<SPIRVWord> Ops = {InputVector->getId(), PtrVector->getId(),
Alignment, Mask->getId()};
return BM->addInstTemplate(internal::OpMaskedScatterINTEL, Ops, BB,
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16 changes: 8 additions & 8 deletions test/extensions/INTEL/SPV_INTEL_masked_gather_scatter/intel-gather-scatter.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -42,11 +42,11 @@

; CHECK-LLVM: %[[#VECGATHER:]] = load <4 x ptr addrspace(4)>, ptr
; CHECK-LLVM: %[[#VECSCATTER:]] = load <4 x ptr addrspace(4)>, ptr
; CHECK-LLVM: %[[GATHER:[a-z0-9]+]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> %[[#VECGATHER]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>)
; CHECK-LLVM: call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %[[GATHER]], <4 x ptr addrspace(4)> %[[#VECSCATTER]], i32 4, <4 x i1> splat (i1 true))
; CHECK-LLVM: %[[GATHER:[a-z0-9]+]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> align 4 %[[#VECGATHER]], <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>)
; CHECK-LLVM: call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %[[GATHER]], <4 x ptr addrspace(4)> align 4 %[[#VECSCATTER]], <4 x i1> splat (i1 true))

; CHECK-LLVM-DAG: declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, i32 immarg, <4 x i1>, <4 x i32>)
; CHECK-LLVM-DAG: declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, i32 immarg, <4 x i1>)
; CHECK-LLVM-DAG: declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, <4 x i1>, <4 x i32>)
; CHECK-LLVM-DAG: declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, <4 x i1>)

target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
target triple = "spir"
Expand All @@ -58,14 +58,14 @@ entry:
%arg1 = alloca <4 x ptr addrspace(4)>
%0 = load <4 x ptr addrspace(4)>, ptr %arg0
%1 = load <4 x ptr addrspace(4)>, ptr %arg1
%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> %0, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>)
call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %res, <4 x ptr addrspace(4)> %1, i32 4, <4 x i1> splat (i1 true))
%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> align 4 %0, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>)
call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %res, <4 x ptr addrspace(4)> align 4 %1, <4 x i1> splat (i1 true))
ret void
}

declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, i32, <4 x i1>, <4 x i32>)
declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, <4 x i1>, <4 x i32>)

declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, i32, <4 x i1>)
declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, <4 x i1>)

!llvm.module.flags = !{!0}
!opencl.spir.version = !{!1}
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