This repository contains two implementations of a phase-locked loop (PLL) on a FPGA (field-programmable gate array). We use the Labview graphical programming environment to generate FPGA binary code and a PC interface.
The algorithm is a Costas loop, inspired by an example by azheng in the Labview Community Examples Forum.
A voltage controlled oscillator (VCO) generates a sine and a cosine. Each is multiplied by the input signal and low pass filtered. The atan2 is calculated to get the phase difference between the VCO and the input signal. A PI controller tries to minimize this phase difference by applying an offset to the VCO.
We use these PLLs to recover the phase of an analog voltage signal. The signal is a superposition of two or three harmonic oscillations of different frequencies in the 10 kHz to 100 kHz frequency range. Three PLLs lock on to the phases of these harmonic signals. Each PLL updates its phase estimate with each sample of the ADC. We interpolate successive phase values on a faster time scale to reduce jitter in the recovered phase zero crossing at which a TTL trigger is generated.
This is part of the reference generation in our setup for fluorescence-detected two-dimensional electronic spectroscopy as described in the following publications:
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Sanchayeeta Jana, Simon Durst, Markus Lippitz: Fluorescence-Detected Two-Dimensional Electronic Spectroscopy of a Single Molecule, Nano Letters, 24, 12576-12581 (2024), doi: 10.1038/s41598-023-33654-6, arxiv: 2407.09200
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Sanchayeeta Jana, Simon Durst, Lucas Ludwig, Markus Lippitz: Overcoming experimental obstacles in two-dimensional spectroscopy of a single molecule, submitted (2025), arxiv: 2502.03924
In the second publication, we characterize the operation of the PLL in the NI USB 7856R implementation.
The NI MyRio is based on a Xilinx Z-7010 and contains an FPGA and a real-time PC. Our code implements the PLL at a high level, which is easier to understand, but leaves a lot of optimization to the compiler. The two sub-variants of our implementation allow either 3 channels and a fixed filter or 2 channels and a variable filter. The ADC operates at 500 kHz and 12 bits. The digital filters are those provided by Labview.
More details are here.
The NI USB-7856R OEM board has a larger FPGA (Kintex-7 160T) and a faster ADC (1 MHz, 16 bit). The PLL algorithm is the same, but is implemented closer to the hardware. We run the core of the PLL in a Single-Cycle Timed Loop (SCTL), which controls the timing more accurately. For this we use the 4-wire handshake. We have also modified the digital filters provided by Labview to work in an SCTL.
More details are here.
We are using here the 2018 version of Labview 32bit. You need the Labview FPGA Module and, for MyRio, the Labview MyRio Toolkit. Newer versions should be able to open and compile the files. With newer versions the FPGA Module is also available for 64bit.
The code is licensed under the MIT license. If you use this code for scientific work, please consider citing one of our publications listed above.