Merge branch 'main' of https://github.com/Lippitz-Lab/PLL-on-FPGA into main

Author: MarkusLippitz

CITATION.cff

@@ -0,0 +1,24 @@
+# This CITATION.cff file was generated with cffinit.
+# Visit https://bit.ly/cffinit to generate yours today!
+
+cff-version: 1.2.0
+title: PLL on FPGA via Labview
+message: >-
+  If you use this software, please cite it using the
+  metadata from this file.
+type: software
+authors:
+  - given-names: Lucas
+    family-names: Ludwig
+    orcid: 'https://orcid.org/0009-0006-1472-0537'
+  - given-names: Markus
+    family-names: Lippitz
+    orcid: 'https://orcid.org/0000-0003-1218-6511'
+repository-code: 'https://github.com/Lippitz-Lab/PLL-on-FPGA'
+abstract: >-
+  This repository contains two implementations of a
+  phase-locked loop (PLL) on a FPGA (field-programmable gate
+  array). We use the Labview graphical programming
+  environment to generate FPGA binary code and a PC
+  interface.
+license: MIT

MyRio/doc/FPGA_main.png

@@ -0,0 +1,11 @@
+# MyRio Implementation
+
+The top level FPGA code is located in `FPGA_main.vi`. 
+
+![Top level FPGA code](MyRio/doc/FPGA_main.png)
+
+The ADC runs at 500 kHz. It is important to keep this timing. The code execution must not take more time than this. A detailed description can be found in the [pdf file](MyRio/Documentation_PLL.pdf).
+
+The project file is the best place to get an overview:
+
+![Lock-In Code](MyRio/doc/project.png)

MyRio/doc/project.png

@@ -0,0 +1,21 @@
+# USB 7856R Implementation
+
+The top level FPGA code is located in `FPGA_main.vi`. It contains several parallel running loops, the most important ones are shown below.
+
+![Top-level FPGA code](USB7856/doc/FPGA_Main_1.png)
+
+
+The ADC runs at 1 MHz and is synchronized to the PLL processing loop, which takes 75 steps at 75 MHz for each sample. Inside the 75 MHz loop are two PLLs and a lock-in amplifier.
+
+
+![PLL code](USB7856/doc/pll-3ch.png)
+
+The PLL in `pll-3ch.vi` (above) is implemented as a [pipeline](https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/optimizing-fpga-vis-using-pipelining-fpga-module.html), which uses the same hardware to compute three successive PLL phases.
+
+The lock-in amplifier in `lockin-3ch.vi` (below) is just a variant of the PLL code. 
+
+![Lock-In code](USB7856/doc/lockin-3ch.png)
+
+The project file is the best place to get an overview:
+
+![Lock-In code](USB7856/doc/project.png)