A Simple Stopwatch implemented on an FPGA board in Verilog HDL.
• Designed and implemented a modular FPGA based digital stopwatch in Verilog targeting Xilinx Zynq-7000 (xc7z007s)
• Developed reusable RTL modules and implemented proper clock domain synchronization and debouncing logic for mechanical push buttons
• Optimized design to use only:
o 107 LUTs (0.74%)
o 190 Flip-Flops (0.66%)
• Implemented multiplexed 7-segment display refresh logic for multi-digit display
• Developed reusable RTL modules: button synchronizer, debouncer, edge detector, BCD counter, time register, and 7-segment display driver
Start / Stop / Reset functionality
Mechanical button synchronization and debouncing
Edge detection for single-cycle pulse generation
Multi-digit 7-segment display with multiplexed refresh
| Module | Description |
|---|---|
button_sync |
2-Flip-Flop synchronizer for metastability protection |
btn_debounce |
Counter-based debounce filter for mechanical push buttons |
button_edge |
Rising-edge detector for single-cycle pulse generation |
tick_tock |
Clock divider for time base generation |
time_counter |
BCD-based time increment logic |
BCD_SSEG |
BCD to 7-segment display encoder |
refresh_rate_counter |
Display multiplexing control logic |
| Resource | Used | Available | Utilization |
|---|---|---|---|
| Slice LUTs | 107 | 14,400 | 0.74% |
| LUT as Logic | 107 | 14,400 | 0.74% |
| LUT as Memory | 0 | 6,000 | 0.00% |
| Slice Registers | 190 | 28,800 | 0.66% |
| Block RAM Tiles | 0 | 50 | 0.00% |
| DSPs | 0 | 66 | 0.00% |
| Bonded IOB | 21 | 100 | 21.00% |
| BUFGCTRL | 1 | 32 | 3.13% |
Stopwatch.mp4
