MIRA Lab — AI4EDA Research Portfolio Template

This document provides an overview of research conducted by MIRA Lab in the field of AI for Electronic Design Automation (AI4EDA). It highlights the lab’s key contributions across multiple fronts, including peer-reviewed publications, open-source tools, and benchmark suites. Together, these works aim to advance intelligent design automation methodologies and foster broader adoption of AI techniques in modern chip design.

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Selected Publications

1. LAMPLACE: LEARNING TO OPTIMIZE CROSS-STAGE METRICS IN MACRO PLACEMENT

• Authors: Zijie Geng, Jie Wang, Ziyan Liu, Siyuan Xu, Zhentao Tang, Shixiong Kai, Mingxuan Yuan, Jianye Hao and Feng Wu
• Published: ICLR 2025 (Oral)
• Keywords: AI4EDA / GNN / Macro Placement
• Summary: Unlike prior macro placement methods that optimize surrogate metrics (e.g., mHPWL, HPWL, congestion), LaMPlace directly targets cross-stage metrics such as WNS and TNS, which truly determine final PPA quality but are difficult to evaluate during placement.
• Code Repository: https://github.com/MIRALab-USTC/AI4EDA-LaMPlace

2. Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms

• Authors: Zhihai Wang，Zijie Geng，Zhaojie Tu ，Jie Wang，Yuxi Qian，Zhexuan Xu，Ziyan Liu，Siyuan Xu，Zhentao Tang，Shixiong Kai，Mingxuan Yuan，Jianye Hao，Bin Li and Feng Wu
• Published: NeurIPS 2025 Datasets and Benchmarks Track
• Keywords: AI4EDA / Benchmark / Placement
• Summary: We introduce ChiPBench, the first fully open-source, reproducible benchmark that covers a complete EDA flow from Verilog to routing, enabling direct evaluation of placement algorithms based on final PPA metrics.
• Code Repository: https://github.com/MIRALab-USTC/ChiPBench

3. High-Performance Arithmetic Circuit Optimization via Differentiable Architecture Search

• Authors: Xilin Xia, Jie Wang, Wanbo Zhang, Zhihai Wang, Mingxuan Yuan, Jianye HAO and Feng Wu
• Published: NeurIPS 2025 (Spotlight)
• Keywords: AI4EDA / Circuit Optimization / Differentiable Architecture Search
• Summary: ARITH-DAS is the first differentiable architecture search framework that directly optimizes fine-grained interconnections in arithmetic circuits without proxies. It achieves substantial improvements in area–delay trade-offs and scales effectively to large real-world AI hardware systems.
• Code Repository: https://github.com/dakfjalka/Arith-DAS

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Open-Source Tools

1. 3d-DREAMPlace

• Summary: Based on DREAMPlace, we incorporated thermal constraints into the optimization objectives, achieving a thermal-aware analytical 3D chip layout algorithm.

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Other Link

• GitHub Organization: https://github.com/MIRALab-USTC