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implement branch instructions
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2 files changed

+98
-8
lines changed

2 files changed

+98
-8
lines changed

src/main/scala/RISCV/Main.scala

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -456,6 +456,102 @@ class Main() extends Module {
456456

457457
printf("[JALR] RS1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
458458
}
459+
460+
// BEQ
461+
is("b000_1100011".U) {
462+
registers.io.read_address_a := decoder.io.rs1;
463+
registers.io.read_address_b := decoder.io.rs2;
464+
465+
when(registers.io.out_a === registers.io.out_b) {
466+
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
467+
}.otherwise {
468+
program_pointer := program_pointer + 1.U;
469+
}
470+
471+
stage := 0.U;
472+
473+
printf("[BEQ] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, decoder.io.immediate);
474+
}
475+
476+
// BNEQ
477+
is("b001_1100011".U) {
478+
registers.io.read_address_a := decoder.io.rs1;
479+
registers.io.read_address_b := decoder.io.rs2;
480+
481+
when(registers.io.out_a =/= registers.io.out_b) {
482+
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
483+
}.otherwise {
484+
program_pointer := program_pointer + 1.U;
485+
}
486+
487+
stage := 0.U;
488+
489+
printf("[BNEQ] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, decoder.io.immediate);
490+
}
491+
492+
// BLT
493+
is("b100_1100011".U) {
494+
registers.io.read_address_a := decoder.io.rs1;
495+
registers.io.read_address_b := decoder.io.rs2;
496+
497+
when(registers.io.out_a.asSInt < registers.io.out_b.asSInt) {
498+
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
499+
}.otherwise {
500+
program_pointer := program_pointer + 1.U;
501+
}
502+
503+
stage := 0.U;
504+
505+
printf("[BLT] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, decoder.io.immediate);
506+
}
507+
508+
// BGE
509+
is("b101_1100011".U) {
510+
registers.io.read_address_a := decoder.io.rs1;
511+
registers.io.read_address_b := decoder.io.rs2;
512+
513+
when(registers.io.out_a.asSInt >= registers.io.out_b.asSInt) {
514+
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
515+
}.otherwise {
516+
program_pointer := program_pointer + 1.U;
517+
}
518+
519+
stage := 0.U;
520+
521+
printf("[BGE] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, decoder.io.immediate);
522+
}
523+
524+
// BLTU
525+
is("b110_1100011".U) {
526+
registers.io.read_address_a := decoder.io.rs1;
527+
registers.io.read_address_b := decoder.io.rs2;
528+
529+
when(registers.io.out_a < registers.io.out_b) {
530+
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
531+
}.otherwise {
532+
program_pointer := program_pointer + 1.U;
533+
}
534+
535+
stage := 0.U;
536+
537+
printf("[BLTU] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, decoder.io.immediate);
538+
}
539+
540+
// BGEU
541+
is("b111_1100011".U) {
542+
registers.io.read_address_a := decoder.io.rs1;
543+
registers.io.read_address_b := decoder.io.rs2;
544+
545+
when(registers.io.out_a >= registers.io.out_b) {
546+
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
547+
}.otherwise {
548+
program_pointer := program_pointer + 1.U;
549+
}
550+
551+
stage := 0.U;
552+
553+
printf("[BGEU] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, decoder.io.immediate);
554+
}
459555
}
460556
}
461557

src/test/scala/RISCV/MainSpec.scala

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -15,23 +15,17 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
1515
dut.clock.step(1);
1616

1717
dut.io.debug_write.poke(true.B);
18-
dut.io.debug_write_data.poke("b000000000000_00001_000_00001_1100111".U(32.W));
18+
dut.io.debug_write_data.poke("b000000000111_00000_000_00010_0010011".U(32.W));
1919
dut.io.debug_write_addressess.poke(1.U);
2020

2121
dut.clock.step(1);
2222

2323
dut.io.debug_write.poke(true.B);
24-
dut.io.debug_write_data.poke("b000000000110_00000_000_00010_0010011".U(32.W));
24+
dut.io.debug_write_data.poke("b0000000_00010_00001_001_00010_1100011".U(32.W));
2525
dut.io.debug_write_addressess.poke(2.U);
2626

2727
dut.clock.step(1);
2828

29-
dut.io.debug_write.poke(true.B);
30-
dut.io.debug_write_data.poke("b000000000111_00000_000_00010_0010011".U(32.W));
31-
dut.io.debug_write_addressess.poke(3.U);
32-
33-
dut.clock.step(1);
34-
3529
dut.io.debug_write.poke(false.B);
3630
dut.io.execute.poke(true.B);
3731

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