implement jalr

Author: outercloudstudio

documentation/Modules/Hart.md

@@ -40,7 +40,7 @@ Currently only the `LW` instruction uses stage 2, since in stage 1 `LW` requests
 - [ ] SH
 - [x] SW
 - [x] JAL
-- [ ] JALR
+- [x] JALR
 - [ ] BEQ
 - [ ] BNE
 - [ ] BLT

src/main/scala/RISCV/Main.scala

@@ -442,6 +442,20 @@ class Main() extends Module {
 
                     printf("[JAL] Rd: %d Immediate: %b\n", decoder.io.rd, decoder.io.immediate);
                 }
+
+                // JALR
+                is("b000_1100111".U) { 
+                    registers.io.read_address_a := decoder.io.rs1;
+
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    registers.io.in := program_pointer + 1.U;
+
+                    program_pointer := (registers.io.out_a.zext + decoder.io.immediate.asSInt).asUInt;
+                    stage := 0.U;
+
+                    printf("[JALR] RS1: %d Rd: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rd, decoder.io.immediate);
+                }
             }
         }
 

src/test/scala/RISCV/MainSpec.scala

@@ -9,13 +9,13 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
   "Main should execute LUI correctly" in {
     simulate(new Main()) { dut =>
       dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b000000000110_00000_000_00001_0010011".U(32.W));
+      dut.io.debug_write_data.poke("b000000000011_00000_000_00001_0010011".U(32.W));
       dut.io.debug_write_addressess.poke(0.U);
 
       dut.clock.step(1);
 
       dut.io.debug_write.poke(true.B);
-      dut.io.debug_write_data.poke("b00000000001000000000_00001_1101111".U(32.W));
+      dut.io.debug_write_data.poke("b000000000000_00001_000_00001_1100111".U(32.W));
       dut.io.debug_write_addressess.poke(1.U);
 
       dut.clock.step(1);