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implenet sb and sh instructions
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src/main/scala/RISCV/Main.scala

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,39 @@ class Main() extends Module {
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printf("[LW] Rs1: %d Immediate: %b\n", decoder.io.rs1, registers.io.out_a + decoder.io.immediate);
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}
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// SB
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is("b000_0100011".U) {
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registers.io.read_address_a := decoder.io.rs1;
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registers.io.read_address_b := decoder.io.rs2;
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memory.writePorts(0).enable := true.B;
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memory.writePorts(0).address := registers.io.out_a + decoder.io.immediate;
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memory.writePorts(0).data := registers.io.out_b(7,0);
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program_pointer := program_pointer + 4.U;
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stage := 0.U;
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printf("[SB] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, registers.io.out_a + decoder.io.immediate);
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}
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// SH
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is("b001_0100011".U) {
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registers.io.read_address_a := decoder.io.rs1;
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registers.io.read_address_b := decoder.io.rs2;
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memory.writePorts(0).enable := true.B;
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memory.writePorts(0).address := registers.io.out_a + decoder.io.immediate;
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memory.writePorts(0).data := registers.io.out_b(7,0);
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memory.writePorts(1).enable := true.B;
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memory.writePorts(1).address := registers.io.out_a + decoder.io.immediate + 1.U;
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memory.writePorts(1).data := registers.io.out_b(15,8);
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program_pointer := program_pointer + 4.U;
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stage := 0.U;
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printf("[SH] Rs1: %d Rs2: %d Immediate: %b\n", decoder.io.rs1, decoder.io.rs2, registers.io.out_a + decoder.io.immediate);
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}
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// SW
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is("b010_0100011".U) {
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registers.io.read_address_a := decoder.io.rs1;

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