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implement lb and lh
1 parent daec539 commit d835ea6

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src/main/scala/RISCV/Main.scala

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,28 @@ class Main() extends Module {
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rd_buffer := decoder.io.rd;
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switch(decoder.io.operation) {
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// LB
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is("b000_0000011".U) {
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registers.io.read_address_a := decoder.io.rs1;
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memory.readPorts(4).enable := true.B;
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memory.readPorts(4).address := registers.io.out_a + decoder.io.immediate;
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printf("[LB] Rs1: %d Immediate: %b\n", decoder.io.rs1, registers.io.out_a + decoder.io.immediate);
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}
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// LH
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is("b001_0000011".U) {
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registers.io.read_address_a := decoder.io.rs1;
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memory.readPorts(4).enable := true.B;
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memory.readPorts(4).address := registers.io.out_a + decoder.io.immediate;
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memory.readPorts(5).enable := true.B;
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memory.readPorts(5).address := registers.io.out_a + decoder.io.immediate + 1.U;
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printf("[LH] Rs1: %d Immediate: %b\n", decoder.io.rs1, registers.io.out_a + decoder.io.immediate);
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}
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// LW
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is("b010_0000011".U) {
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registers.io.read_address_a := decoder.io.rs1;
@@ -650,6 +672,28 @@ class Main() extends Module {
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stage := 0.U;
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switch(operation_buffer) {
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// LB
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is("b000_0000011".U) {
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registers.io.write_address := rd_buffer;
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registers.io.write_enable := true.B;
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registers.io.in := Fill(24, memory.readPorts(4).data(7)) ## memory.readPorts(4).data;
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program_pointer := program_pointer + 4.U;
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printf("[LB] Rd: %d Data: %b\n", rd_buffer, Fill(24, memory.readPorts(4).data(7)) ## memory.readPorts(4).data);
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}
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// LH
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is("b001_0000011".U) {
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registers.io.write_address := rd_buffer;
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registers.io.write_enable := true.B;
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registers.io.in := Fill(16, memory.readPorts(5).data(7)) ## memory.readPorts(5).data ## memory.readPorts(4).data;
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program_pointer := program_pointer + 4.U;
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printf("[LH] Rd: %d Data: %b\n", rd_buffer, Fill(16, memory.readPorts(5).data(7)) ## memory.readPorts(5).data ## memory.readPorts(4).data);
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}
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// LW
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is("b010_0000011".U) {
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registers.io.write_address := rd_buffer;

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