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implement lbu and lhu
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src/main/scala/RISCV/Main.scala

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,28 @@ class Main() extends Module {
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printf("[LW] Rs1: %d Immediate: %b\n", decoder.io.rs1, registers.io.out_a + decoder.io.immediate);
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}
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// LBU
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is("b100_0000011".U) {
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registers.io.read_address_a := decoder.io.rs1;
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memory.readPorts(4).enable := true.B;
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memory.readPorts(4).address := registers.io.out_a + decoder.io.immediate;
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printf("[LBU] Rs1: %d Immediate: %b\n", decoder.io.rs1, registers.io.out_a + decoder.io.immediate);
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}
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// LHU
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is("b101_0000011".U) {
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registers.io.read_address_a := decoder.io.rs1;
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memory.readPorts(4).enable := true.B;
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memory.readPorts(4).address := registers.io.out_a + decoder.io.immediate;
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memory.readPorts(5).enable := true.B;
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memory.readPorts(5).address := registers.io.out_a + decoder.io.immediate + 1.U;
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printf("[LHU] Rs1: %d Immediate: %b\n", decoder.io.rs1, registers.io.out_a + decoder.io.immediate);
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}
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// SB
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is("b000_0100011".U) {
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registers.io.read_address_a := decoder.io.rs1;
@@ -638,6 +660,28 @@ class Main() extends Module {
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printf("[LW] Rd: %d Data: %b\n", rd_buffer, memory.readPorts(7).data ## memory.readPorts(6).data ## memory.readPorts(5).data ## memory.readPorts(4).data);
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}
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// LBU
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is("b100_0000011".U) {
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registers.io.write_address := rd_buffer;
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registers.io.write_enable := true.B;
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registers.io.in := 0.U(24.W) ## memory.readPorts(4).data;
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program_pointer := program_pointer + 4.U;
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printf("[LBU] Rd: %d Data: %b\n", rd_buffer, 0.U(24.W) ## memory.readPorts(4).data);
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}
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// LHU
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is("b101_0000011".U) {
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registers.io.write_address := rd_buffer;
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registers.io.write_enable := true.B;
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registers.io.in := 0.U(16.W) ## memory.readPorts(5).data ## memory.readPorts(4).data;
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program_pointer := program_pointer + 4.U;
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printf("[LHU] Rd: %d Data: %b\n", rd_buffer, 0.U(16.W) ## memory.readPorts(5).data ## memory.readPorts(4).data);
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}
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}
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}
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}

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