More cleanup

Author: outercloudstudio

src/main/scala/RISCV/ALU.scala

@@ -4,6 +4,9 @@ import chisel3._
 import chisel3.util._
 import _root_.circt.stage.ChiselStage
 
+/**
+  * @param width Bit width (default: 32 bits)
+  */
 class ALU(val width: Int = 32) extends Module {
     val io = IO(new Bundle {
         val add = Input(Bool());

src/main/scala/RISCV/Hart.scala

@@ -5,15 +5,14 @@ import _root_.circt.stage.ChiselStage
 import scala.math._
 
 /**
-  * The Hardware thread "Hart" used in the 
+  * The Hardware thread "Hart" used in the RISC-V spec
   *
   * @param width Bit width (default: 32 bits)
   */
-  
 class Hart(val width: Int = 32) extends Module {
     val io = IO(new Bundle {})
 
-    val program_pointer = RegInit(0.U(width.W))
+    val program_pointer = Module(new PC());
 
     val registers = Module(new Registers());
 }

src/main/scala/RISCV/Main.scala

@@ -1,10 +1,7 @@
-// See README.md for license details.
-
 package RISCV
 
 import chisel3._
 import chisel3.util._
-// _root_ disambiguates from packages like chisel3.util.circt if imported
 import _root_.circt.stage.ChiselStage
 import scala.math._
 import os.read

src/main/scala/RISCV/PC.scala

@@ -1,9 +1,6 @@
-// See README.md for license details.
-
 package RISCV
 
 import chisel3._
-// _root_ disambiguates from packages like chisel3.util.circt if imported
 import _root_.circt.stage.ChiselStage
 import scala.math._
 

src/main/scala/RISCV/Registers.scala

@@ -1,20 +1,10 @@
-// See README.md for license details.
-
 package RISCV
 
 import chisel3._
-// _root_ disambiguates from packages like chisel3.util.circt if imported
 import _root_.circt.stage.ChiselStage
 import scala.math._
 
-/**
-  * A simple register file module with parameterizable width and number of registers.
-  * 
-  * TODO: Set up two simultaneous read ports
-  */
-
 class Registers() extends Module {
-    // Define input/output interface
     val io = IO(new Bundle {
         val in  = Input(UInt(32.W))
         val write_addr = Input(UInt(5.W))
@@ -23,14 +13,11 @@ class Registers() extends Module {
         val out = Output(UInt(32.W))
     })
 
-    // Internal register array
     val regs = RegInit(VecInit(Seq.fill(32.toInt)(0.U(32.W))))
 
-    // Default output
     io.out := regs(io.read_addr)
 
-    when(io.write_enable && (io.write_addr =/= 0.U)) { // Write operation; Register 0 is hardwired to 0
+    when(io.write_enable && (io.write_addr =/= 0.U)) {
         regs(io.write_addr) := io.in
-        //printf(p"Writing value ${io.in} to register ${io.write_addr}\n")
     }
 }

src/test/scala/RISCV/MainSpec.scala

@@ -1,5 +1,3 @@
-// See README.md for license details.
-
 package RISCV
 
 import chisel3._

src/test/scala/RISCV/RegistersSpec.scala

@@ -1,5 +1,3 @@
-// See README.md for license details.
-
 package RISCV
 
 import chisel3._