v0.0.2

verilog-library

Adder

Full Adder

full_adder(input A, B, Ci, output Co, S)

Equivalent module:

module full_adder(input A, B, Ci, output Co, S);
  assign S = A ^ B ^ Ci;
  assign Co = (A & B) | ((A ^ B) & Ci);
endmodule

module full_adder(input A, B, Ci, output Co, S);
  assign {Co, S} = A + B + Ci;
endmodule

Half Adder

half_adder(input A, B, output C, S);

Flip Flop

RS Flip Flop

rs_flip_flop(input R, S, output Q, Qbar);