DD2_Verilog_netList_enhancer

Acknowledgments:
1. This Project was done for Digital Design 2 course under supervision of Dr Mohamed Shalan
2. This Project was done under the umberlla of the csce department at The American University in Cairo

Assumptions:
1. fixed input transition (intermediate transition).
2. we are dealing with single output cells.
3. the delays are calculated for each cell with the related pin that has the highest delay.
4. the delay calculated is the sum of the delays of all the cell individually, no partiqular path is traced.

How to use:
change the .v file name in the code and the .lib if needed
the .lib file name should be changed in two loactions, inside the class and inside the main code
the .v file name should only be changed inside the main code
run the code
choose the optimizing methodology
specify the maximum fan out
the program will run and display at the end the frequency of each cell before and after alterations
the total delay before and after alterations will also be displayed automatically. The Final Netlist
will be saved in a file named output.v that will be present in the running path.

Limitations:
- depending on the provided liberity file, sizing up may not be possible as large sizes of the cells aren't
available in the liberity
- the total cell delay may actually increase after modifications since we aim to improve individual cell
delays and signals, so added cells or buffers my increase the accumilative cell delay
- the program can't handle verilog netlists that contain cells with more than one output, it handles them as
single-output cells and neglects all additional outputs
Dependencies: - the liberty-parser library requires the installment of some additional python libraries (can be done through terminal): ='lark-parser' ='numpy' ='sympy'