edits

Author: TylerMSFT

docs/build/arm-exception-handling.md

@@ -1,8 +1,7 @@
 ---
 description: "Learn more about: ARM Exception Handling"
 title: "ARM Exception Handling"
-ms.date: 12/15/2021
-ms.assetid: fe0e615f-c033-4ad5-97f4-ff96af45b201
+ms.date: 04/08/2025
 ---
 # ARM Exception Handling
 

docs/build/arm64-windows-abi-conventions.md

@@ -121,11 +121,7 @@ Like AArch32, the AArch64 specification provides three system-controlled "thread
 
 You can determine if an ARM CPU supports exceptions by writing a value that enables exceptions to the FPCR register and then reading it back. If the CPU supports floating-point exceptions, the bits corresponding to the supported exceptions remain set, while the bits corresponding to unsupported exceptions are reset by the CPU.
 
-For ARM CPUs that support IEEE floating-point exceptions, the behavior on Windows is as follows:
-
-- **ARM32**: Windows doesn't support floating-point exceptions.
-- **ARM64**: For processor variants that support hardware floating-point exceptions, Windows delivers them.
-- **ARM64EC**: For processor variants that support hardware floating-point exceptions, Windows catches these exceptions and disables them in the FPCR register. This ensures consistent behavior across different processor variants.
+On ARM64, Windows delivers exceptions for those processors that support hardware floating-point exceptions.
 
 - The [`_set_controlfp`](/cpp/c-runtime-library/reference/controlfp-s) function on ARM platforms correctly changes the FPCR register when unmasking floating-point exceptions. However, instead of raising an unmasked exception, Windows resets the FPCR register to its defaults every time an FP exception is about to be raised.
 

docs/build/arm64ec-windows-abi-conventions.md

@@ -92,6 +92,12 @@ Special helper routines like `__chkstk_arm64ec` use custom calling conventions a
 
 ARM64EC follows the same struct packing rules used for x64 to ensure interoperability between ARM64EC code and x64 code. For more information and examples of x64 struct packing, see [Overview of x64 ABI conventions](x64-software-conventions.md).
 
+## Floating-point exceptions
+
+You can determine if an ARM CPU supports exceptions by writing a value that enables exceptions to the FPCR register and then reading it back. If the CPU supports floating-point exceptions, the bits corresponding to the supported exceptions remain set, while the bits corresponding to unsupported exceptions are reset by the CPU.
+
+For ARM64EC, Windows catches processor floating-point exceptions and disables them in the FPCR register. This ensures consistent behavior across different processor variants.
+
 ## Emulation helper ABI routines
 
 ARM64EC code and [thunks](#thunks) use emulation helper routines to transition between x64 and ARM64EC functions.

docs/build/x64-software-conventions.md

@@ -1,7 +1,7 @@
 ---
 description: "Learn more about: x64 ABI conventions"
 title: "x64 ABI conventions"
-ms.date: 04/07/2025
+ms.date: 03/28/2025
 helpviewer_keywords: ["x64 coding conventions", "x64 abi", "Visual C++, x64 calling conventions"]
 ---
 # Overview of x64 ABI conventions