This project aims to explore and implement a system to classify Hand Writing Digit Images using the FPGA (Basys3) board and a camera (OV7670). The system performs real-time image classification leveraging the capabilities of an FPGA.
The purpose of this project is to:
✅ Design and implement a hardware system for hand writing digit classification.
✅ Integrate image capture and processing using the OV7670 camera module.
✅ Study and implement an Artificial Intelligence model in digital logic design.
Handwriting Digit Classification involves recognizing and categorizing handwritten numerical digits (0-9) from input images. This is a core problem in computer vision with applications in Optical Character Recognition (OCR) and automated data entry systems.
- Camera Module (OV7670): Captures grayscale images of handwritten digits.
- Implements image preprocessing to optimize for classification.
- Pre-trained Neural Network (MLP) on FPGA: Performs digit classification.
- Uses matrix multiplications and activation functions designed for efficient execution on FPGA.
- Basys3 FPGA Board: Implements both the digit classification and the interface for real-time operations.
- VGA Output: Displays classification results on a connected monitor.
- Hardware: Basys3 FPGA, OV7670 Camera Module
- Programming Language: Verilog HDL
- Tools: Xilinx Vivado, ModelSim
- Development Environment: Windows/Linux
Follow the instructions below to set up and run the project on your FPGA board.
git clone https://github.com/Muaykillz/Final-Project-CPE222.git
cd Classify-ModelOpen the project in Xilinx Vivado and follow these steps:
- Load the
..wait..xprfile. - Run Synthesis and Implementation.
- Generate the bitstream.
- Connect the Basys3 board to your PC via USB.
- Use Vivado to program the FPGA with the generated bitstream file.
- Ensure the OV7670 camera module is connected to the board.
- Display the VGA output on a monitor.
- Place a handwritten digit in front of the camera.
- Observe the classification result displayed on the screen.
✅ Real-time image classification using FPGA.
✅ Integration of OV7670 camera for live image capture.
✅ VGA output for displaying classification results.
✅ Pre-trained neural network(MLP) implemented directly in Verilog.
This project was developed as part of the coursework for CPE at King Mongkut's University of Technology Thonburi (KMUTT). Special thanks to our professors and peers for their guidance and support.
📧 Contact Us:
| Muaykillz
| NongChugra
| Feen0305
| DarkTouiZ