Digital_System_Design_Lab

This repository contains lab assignments for the Digital System Design (DSD) course at University of Engineering and Technology (UET), for Session 2023 Section A.

Lab Assignments

• Lab_no_1: [Patched a NOT gate on Breadboard to find the propagation Delay]
• Lab_no_2: [RTL and Texrbench code to know QuestaSim]
• Lab_no_3: [RTL code to know Vivado]
• Lab_no_4: [RTL and Testbench for Full Adder ]
• Lab_no_5: [Combinational Circuit for Seven Segemnt Display]
• Lab_no_7: [Sequentail Circuit for Seven Segemnt Display]

Technologies Used

• SystemVerilog: For Design And Testbench
• QuestaSim: For Simulation
• Nexys A7 : For Hardware testing
• Vivado: For Designing Circuits for FPGA

Getting Started

To run the SystemVerilog files:

1. Ensure you have QuestaSim or Vivado installed.

2. Clone this repository:

   git clone https://github.com/MuhammadYousaf79/DSD_2023_EE_011.git

3. Navigate to the desired lab directory:

   cd DSD_2023_EE_011/Lab_no_X