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Unable to run ATACS

Status: Open.

#69 In MyersResearchGroup/ATACS;

· tramyn opened on Jul 11, 2018

Incorrect results for constant outputs

Status: Open.

#66 In MyersResearchGroup/ATACS;

· cjmyers opened on Jun 28, 2018

Multicube covers should not be split in Verilog output

Status: Open.

#65 In MyersResearchGroup/ATACS;

· cjmyers opened on Jun 28, 2018

Add notion of internal signal type

Status: Open.

#64 In MyersResearchGroup/ATACS;

· cjmyers opened on Jun 28, 2018

Better initial state format

Status: Open.

#63 In MyersResearchGroup/ATACS;

· cjmyers opened on Jun 28, 2018

Verilog output with assign statements

Status: Open.

#62 In MyersResearchGroup/ATACS;

· danilovesky opened on Apr 18, 2017

Segmentation fault at synthesis of VME bus controller

Status: Open.

#61 In MyersResearchGroup/ATACS;

· danilovesky opened on Apr 14, 2017

New-line is OS specific in the parser

Status: Open.

#59 In MyersResearchGroup/ATACS;

· danilovesky opened on Apr 14, 2017

FEATURE: ATACS needs a help file

Documentation

Status: Open.

#58 In MyersResearchGroup/ATACS;

· buggsley opened on Nov 7, 2016

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7.0

un1S bug in combo gate generation

Status: Open.

#57 In MyersResearchGroup/ATACS;

· buggsley opened on Nov 7, 2016

reset automatically

Status: Open.

#56 In MyersResearchGroup/ATACS;

· buggsley opened on Nov 7, 2016

CSC problems

Status: Open.

#55 In MyersResearchGroup/ATACS;

· buggsley opened on Nov 7, 2016