[TRTLLM-9465][fix] Swap TP-CP grouping order #10350
Conversation
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
from
fa73294 to
5fda479
Compare
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
2 times, most recently
from
98c4683 to
767f2d9
Compare
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
from
dfd940b to
d9384e8
Compare
brb-nv
requested review from
nv-yilinf and
schetlur-nv
and removed request for
nv-yilinf
📝 WalkthroughWalkthroughThis PR fundamentally reworks rank decomposition and indexing across distributed tensor/context parallelism dimensions. The calculation of Changes
Estimated code review effort🎯 4 (Complex) | ⏱️ ~60 minutes Possibly related PRs
Suggested reviewers
Pre-merge checks and finishing touches❌ Failed checks (1 warning)
✅ Passed checks (2 passed)
✨ Finishing touches
Thanks for using CodeRabbit! It's free for OSS, and your support helps us grow. If you like it, consider giving us a shout-out. Comment |
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
from
af69ed7 to
464ee46
Compare
![coderabbitai[bot]](https://avatars.githubusercontent.com/in/347564?s=60&v=4){kind=small}
There was a problem hiding this comment.
Actionable comments posted: 0
🧹 Nitpick comments (3)
cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp (1)
63-96: TP rank decomposition now consistent with TP×CP layoutComputing
selfTpRankas(selfIdx % (tensorParallelism * selfCpSize)) / selfCpSizecorrectly recovers the TP index from app * (tp * cp) + tp * cp + cprank layout and fixes the previous CP‑agnostic interpretation. Behavior is unchanged forCP=1and correct forCP>1.You might optionally mark
selfCpSize/selfTpRankasconst intfor clarity, but that’s not required.cpp/tensorrt_llm/batch_manager/cacheFormatter.cpp (1)
157-168: CP‑aware TP rank fixes duplicate‑head routing with CP>1Using
selfTpRank = (selfIdx % (tensorParallelism * selfCpSize)) / selfCpSizemakes the TP rank computation consistent with the new TP×CP rank layout, so the duplicate‑head factor and DP‑group arithmetic behave correctly when CP is enabled. This aligns with the MLA path and mapping changes.As above, you could mark
selfCpSize/selfTpRankasconst intfor readability if you like.tests/integration/defs/accuracy/test_disaggregated_serving.py (1)
915-915: Consider removing commented debug code.The commented
print_iter_loglines (Lines 915, 934) appear to be debug artifacts. Consider removing them to keep the test code clean.🔎 Proposed cleanup
"cache_transceiver_config": { "backend": "UCX" }, - # "print_iter_log": True, } gen_server_config = { ... "cache_transceiver_config": { "backend": "UCX" }, - # "print_iter_log": True, }Also applies to: 934-934
📜 Review details
Configuration used: Path: .coderabbit.yaml
Review profile: CHILL
Plan: Pro
📒 Files selected for processing (11)
cpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cppcpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cutensorrt_llm/_torch/device_mesh.pytensorrt_llm/mapping.pytensorrt_llm/models/modeling_utils.pytests/integration/defs/accuracy/test_disaggregated_serving.pytests/integration/test_lists/qa/llm_function_core.txttests/integration/test_lists/test-db/l0_dgx_b200.ymltests/integration/test_lists/test-db/l0_gb200_multi_gpus.ymltests/unittest/others/test_mapping.py
💤 Files with no reviewable changes (1)
- tests/integration/test_lists/test-db/l0_gb200_multi_gpus.yml
🧰 Additional context used
📓 Path-based instructions (3)
**/*.py
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
**/*.py: Code developed for TensorRT-LLM should conform to Python 3.8+
Indent Python code with 4 spaces. Do not use tabs
Always maintain the namespace when importing in Python, even if only one class or function from a module is used
Python files should use snake_case naming:some_file.py
Python classes should use PascalCase naming:class SomeClass
Python functions and methods should use snake_case naming:def my_awesome_function():
Python local variables should use snake_case naming:my_variable = ...
Python variable names that start with a number should be prefixed with 'k':k_99th_percentile = ...
Python global variables should use upper snake_case with prefix 'G':G_MY_GLOBAL = ...
Python constants should use upper snake_case naming:MY_CONSTANT = ...
Avoid shadowing variables declared in an outer scope in Python
Initialize all externally visible members of a Python class in the constructor
For Python interfaces that may be used outside a file, prefer docstrings over comments
Python comments should be reserved for code within a function, or interfaces that are local to a file
Use Google style docstrings in Python for classes and functions, which can be parsed by Sphinx
Python attributes and variables can be documented inline with type and description
Avoid using reflection in Python when functionality can be easily achieved without reflection
When using try-except blocks in Python, limit the except to the smallest set of errors possible
When using try-except blocks in Python to handle multiple possible variable types (duck-typing), keep the body of the try as small as possible, using the else block for logic
Files:
tensorrt_llm/_torch/device_mesh.pytensorrt_llm/models/modeling_utils.pytests/unittest/others/test_mapping.pytensorrt_llm/mapping.pytests/integration/defs/accuracy/test_disaggregated_serving.py
**/*.{cpp,h,cu,cuh,py}
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
All TensorRT-LLM Open Source Software code should contain an NVIDIA copyright header that includes the year of its latest meaningful modification
Files:
tensorrt_llm/_torch/device_mesh.pycpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cutensorrt_llm/models/modeling_utils.pytests/unittest/others/test_mapping.pycpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpptensorrt_llm/mapping.pytests/integration/defs/accuracy/test_disaggregated_serving.py
**/*.{cpp,h,cu,cuh}
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
**/*.{cpp,h,cu,cuh}: Closing braces of namespaces should have a comment saying the namespace it closes:} // namespace foo
Preferconstorconstexprvariables over#definewhenever possible, as the latter are not visible to the compiler
A variable that is not modified after its initialization should be declared asconst
For naming of constants in C++, follow the naming section conventions
Except0(only used in comparison for checking signness/existence/emptiness) andnullptr,true,false, all other literals should only be used for variable initialization in C++
Use the Allman indentation style in C++
Put the semicolon for an emptyfororwhileloop in a new line in C++
The statement forming the body of aswitch,while,do .. whileorforstatement shall be a compound statement (use brace-delimited statements) in C++
If and else should always be followed by brace-delimited statements, even if empty or a single statement in C++
C++ filenames should use camel case with first letter lowercase:thisIsASubDirandthisIsAFilename.cpp
All files involved in the compilation of a compilation target (.exe/.so) must have filenames that are case-insensitive unique in C++
All types (including class names) in C++ should use camel case with uppercase first letter:FooBarClass
Local variables, methods and namespaces in C++ should use camel case with first letter lowercase:localFooBar
Non-magic-number global variables that are non-static and not defined in anonymous namespace in C++ should use camel case prefixed by a lower case 'g':gDontUseGlobalFoos
Non-magic-number global variables that are static or defined in an anonymous namespace in C++ should use camel case prefixed by a lower case 's':sMutableStaticGlobal
Locally visible static variables in C++ should use camel case with lowercase prefix 's' as the first letter:static std::once_flag sFlag;
Public, private and protected class member variables in C++ should use camel case prefi...
Files:
cpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cucpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
🧠 Learnings (23)
📓 Common learnings
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:42-49
Timestamp: 2025-09-23T14:58:05.372Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/), the token partitioning intentionally uses ceil-like distribution (same token_per_rank for all ranks) to ensure all ranks launch the same number of blocks. This is required for optimal NCCL device API barrier performance, even though it may launch extra blocks for non-existent tokens on later ranks. Runtime bounds checking in the kernel (blockID validation) handles the overshoot cases.
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: tests/unittest/_torch/multi_gpu/test_nccl_device.py:138-149
Timestamp: 2025-10-13T19:45:03.518Z
Learning: In test_nccl_device.py, the NCCL device AllReduce implementation compares the entire residual tensor on each rank, unlike the UB implementation which compares per-rank chunks. The residual chunking calculations in the test are intentionally overridden to reflect this design difference.
📚 Learning: 2025-08-13T11:07:11.772Z
Learnt from: Funatiq
Repo: NVIDIA/TensorRT-LLM PR: 6754
File: tests/integration/test_lists/test-db/l0_a30.yml:41-47
Timestamp: 2025-08-13T11:07:11.772Z
Learning: In TensorRT-LLM test configuration files like tests/integration/test_lists/test-db/l0_a30.yml, TIMEOUT values are specified in minutes, not seconds.
Applied to files:
tests/integration/test_lists/test-db/l0_dgx_b200.yml
📚 Learning: 2025-08-26T09:49:04.956Z
Learnt from: pengbowang-nv
Repo: NVIDIA/TensorRT-LLM PR: 7192
File: tests/integration/test_lists/test-db/l0_dgx_b200.yml:56-72
Timestamp: 2025-08-26T09:49:04.956Z
Learning: In TensorRT-LLM test configuration files, the test scheduling system handles wildcard matching with special rules that prevent duplicate test execution even when the same tests appear in multiple yaml files with overlapping GPU wildcards (e.g., "*b200*" and "*gb200*").
Applied to files:
tests/integration/test_lists/test-db/l0_dgx_b200.yml
📚 Learning: 2025-09-09T09:40:45.658Z
Learnt from: fredricz-20070104
Repo: NVIDIA/TensorRT-LLM PR: 7645
File: tests/integration/test_lists/qa/llm_function_core.txt:648-648
Timestamp: 2025-09-09T09:40:45.658Z
Learning: In TensorRT-LLM test lists, it's common and intentional for the same test to appear in multiple test list files when they serve different purposes (e.g., llm_function_core.txt for comprehensive core functionality testing and llm_function_core_sanity.txt for quick sanity checks). This duplication allows tests to be run in different testing contexts.
Applied to files:
tests/integration/test_lists/test-db/l0_dgx_b200.ymltests/integration/test_lists/qa/llm_function_core.txt
📚 Learning: 2025-09-17T06:01:01.836Z
Learnt from: fredricz-20070104
Repo: NVIDIA/TensorRT-LLM PR: 7785
File: tests/integration/defs/perf/utils.py:321-333
Timestamp: 2025-09-17T06:01:01.836Z
Learning: In test infrastructure code for disaggregated serving tests, prefer logging errors and continuing execution rather than raising exceptions on timeout, to avoid disrupting test cleanup and causing cascading failures.
Applied to files:
tests/integration/test_lists/test-db/l0_dgx_b200.yml
📚 Learning: 2025-07-28T17:06:08.621Z
Learnt from: moraxu
Repo: NVIDIA/TensorRT-LLM PR: 6303
File: tests/integration/test_lists/qa/examples_test_list.txt:494-494
Timestamp: 2025-07-28T17:06:08.621Z
Learning: In TensorRT-LLM testing, it's common to have both CLI flow tests (test_cli_flow.py) and PyTorch API tests (test_llm_api_pytorch.py) for the same model. These serve different purposes: CLI flow tests validate the traditional command-line workflow, while PyTorch API tests validate the newer LLM API backend. Both are legitimate and should coexist.
Applied to files:
tests/integration/test_lists/test-db/l0_dgx_b200.yml
📚 Learning: 2025-09-17T02:48:52.732Z
Learnt from: tongyuantongyu
Repo: NVIDIA/TensorRT-LLM PR: 7781
File: tests/integration/test_lists/waives.txt:313-313
Timestamp: 2025-09-17T02:48:52.732Z
Learning: In TensorRT-LLM, `tests/integration/test_lists/waives.txt` is specifically for waiving/skipping tests, while other test list files like those in `test-db/` and `qa/` directories are for different test execution contexts (pre-merge, post-merge, QA tests). The same test appearing in both waives.txt and execution list files is intentional - the test is part of test suites but will be skipped due to the waiver.
Applied to files:
tests/integration/test_lists/qa/llm_function_core.txt
📚 Learning: 2025-08-06T13:58:07.506Z
Learnt from: galagam
Repo: NVIDIA/TensorRT-LLM PR: 6487
File: tests/unittest/_torch/auto_deploy/unit/singlegpu/test_ad_trtllm_bench.py:1-12
Timestamp: 2025-08-06T13:58:07.506Z
Learning: In TensorRT-LLM, test files (files under tests/ directories) do not require NVIDIA copyright headers, unlike production source code files. Test files typically start directly with imports, docstrings, or code.
Applied to files:
tests/integration/test_lists/qa/llm_function_core.txt
📚 Learning: 2025-09-23T14:58:05.372Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:42-49
Timestamp: 2025-09-23T14:58:05.372Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/), the token partitioning intentionally uses ceil-like distribution (same token_per_rank for all ranks) to ensure all ranks launch the same number of blocks. This is required for optimal NCCL device API barrier performance, even though it may launch extra blocks for non-existent tokens on later ranks. Runtime bounds checking in the kernel (blockID validation) handles the overshoot cases.
Applied to files:
cpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cutensorrt_llm/models/modeling_utils.pycpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-08-19T12:45:11.997Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 7033
File: tensorrt_llm/_torch/pyexecutor/model_engine.py:0-0
Timestamp: 2025-08-19T12:45:11.997Z
Learning: In tensorrt_llm/_torch/pyexecutor/model_engine.py, DoRA (Delta Orthogonal Rank Adaptation) functionality was removed from the PyTorch flow to eliminate issues with inverted DoRA detection logic. The original is_dora condition was checking if scaling_vec_pointer == 0, which was potentially incorrect.
Applied to files:
cpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cutensorrt_llm/models/modeling_utils.py
📚 Learning: 2025-08-14T21:04:50.248Z
Learnt from: thorjohnsen
Repo: NVIDIA/TensorRT-LLM PR: 6910
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-14T21:04:50.248Z
Learning: In KV cache onboarding logic during prefill in cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, when calculating which blocks fall within the attention window, use getTokensPerBlock() to advance token indices rather than block->getUniqueTokens().size(), because the calculation needs to consider the post-prefill state where blocks will be filled to capacity, not their current token count.
Applied to files:
cpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cucpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-08-21T09:41:49.347Z
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6768
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:2010-2045
Timestamp: 2025-08-21T09:41:49.347Z
Learning: In cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, updateSequenceCacheBlockOffsets is specifically for updating bookkeeping when blocks are added during the context phase, not for refreshing offsets after detach operations. During detach operations, GenerationRequest::removeFrontBlock handles the necessary cache block bookkeeping internally.
Applied to files:
cpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cucpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation.
Applied to files:
cpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cutensorrt_llm/models/modeling_utils.pycpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.
Applied to files:
cpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cutensorrt_llm/models/modeling_utils.pycpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-08-26T06:07:02.166Z
Learnt from: shaharmor98
Repo: NVIDIA/TensorRT-LLM PR: 7231
File: tensorrt_llm/_torch/pyexecutor/_util.py:504-509
Timestamp: 2025-08-26T06:07:02.166Z
Learning: In tensorrt_llm/_torch/pyexecutor/_util.py, when calling model_engine.set_lora_model_config(), pass model_binding_config.mlp_hidden_size directly without multiplying by mapping.tp_size, as the mlp_hidden_size from get_bindings_model_config() is already the per-TP rank value needed for LoRA weight packaging.
Applied to files:
tensorrt_llm/models/modeling_utils.py
📚 Learning: 2025-08-14T06:36:40.701Z
Learnt from: timlee0212
Repo: NVIDIA/TensorRT-LLM PR: 6886
File: tensorrt_llm/_torch/models/modeling_deepseekv3.py:0-0
Timestamp: 2025-08-14T06:36:40.701Z
Learning: In DeepSeek V3 model (tensorrt_llm/_torch/models/modeling_deepseekv3.py), the disagreement between AllReduce.__init__ guard and _compute_mlp_tp_size logic for MNNVL usage is expected by design. The AllReduce component and MLP TP-size computation intentionally use different criteria for MNNVL availability decisions.
Applied to files:
tensorrt_llm/models/modeling_utils.py
📚 Learning: 2025-08-08T04:10:19.038Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6728
File: cpp/tensorrt_llm/plugins/mixtureOfExperts/mixtureOfExpertsPlugin.cpp:966-966
Timestamp: 2025-08-08T04:10:19.038Z
Learning: TensorRT plugins currently don't support padding functionality, and TensorRT is not getting new features (in maintenance mode). This means that duplicating parameters like mExpertHiddenSize in function calls, even with TODO comments, can be acceptable as pragmatic solutions within these constraints.
Applied to files:
tensorrt_llm/models/modeling_utils.py
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Applied to files:
tensorrt_llm/models/modeling_utils.py
📚 Learning: 2025-08-06T08:18:28.669Z
Learnt from: zhengd-nv
Repo: NVIDIA/TensorRT-LLM PR: 6633
File: cpp/tensorrt_llm/batch_manager/dataTransceiverImpl.cpp:145-155
Timestamp: 2025-08-06T08:18:28.669Z
Learning: In cpp/tensorrt_llm/batch_manager/dataTransceiverImpl.cpp, the existing `mMtxForMap` mutex in DataSenderImpl is sufficient to synchronize measurement file operations in the `release` method, as all file operations occur within the same critical section that protects the `mRequestToSession` map access.
Applied to files:
cpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-08-15T06:46:54.897Z
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6767
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-15T06:46:54.897Z
Learning: In cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp addToken function, newly allocated blocks are unshared by design. The beam search path in addToken (when sequence.getNumTokens() > windowSize) is currently broken/non-functional with SWA, so the block allocation doesn't follow a shared-then-unshared pattern.
Applied to files:
cpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-08-20T06:48:45.368Z
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6768
File: cpp/include/tensorrt_llm/batch_manager/kvCacheManager.h:0-0
Timestamp: 2025-08-20T06:48:45.368Z
Learning: In cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, updateSequenceCacheBlockOffsets is only called when adding a sequence, not during detach operations. During detach, the cache block bookkeeping is handled by GenerationRequest::removeFrontBlock.
Applied to files:
cpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-09-23T15:01:00.070Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:15-17
Timestamp: 2025-09-23T15:01:00.070Z
Learning: In TensorRT-LLM NCCL device kernels, the <sstream> header is not needed as an explicit include in config.cu because it's provided transitively through other headers. Local compilation testing confirms this works without the explicit include.
Applied to files:
cpp/tensorrt_llm/batch_manager/cacheFormatter.cppcpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
📚 Learning: 2025-08-20T06:56:02.889Z
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6768
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:577-579
Timestamp: 2025-08-20T06:56:02.889Z
Learning: In cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, maxSequenceLength is now enforced as a non-optional argument in the BlockManager constructor, so concerns about std::nullopt defaulting to 0 are not applicable. When windowSize > maxSequenceLength, a warning should be added instead of handling optional parameter cases.
Applied to files:
cpp/tensorrt_llm/batch_manager/mlaCacheFormatter.cpp
🧬 Code graph analysis (4)
tensorrt_llm/_torch/device_mesh.py (3)
tensorrt_llm/_utils.py (2)
shape(1001-1002)shape(1018-1019)tensorrt_llm/_torch/utils.py (1)
shape(141-142)tensorrt_llm/_torch/distributed/communicator.py (1)
cp_size(56-57)
tensorrt_llm/models/modeling_utils.py (3)
tensorrt_llm/_torch/distributed/communicator.py (2)
tp_size(64-65)cp_size(56-57)tensorrt_llm/runtime/model_runner.py (1)
mapping(825-826)tensorrt_llm/mapping.py (2)
rank(199-200)rank(203-210)
tests/unittest/others/test_mapping.py (1)
tensorrt_llm/mapping.py (13)
tp_group(563-564)pp_group(567-568)cp_group(571-572)is_last_pp_rank(261-262)is_first_cp_rank(288-289)is_last_cp_rank(285-286)prev_pp_rank(273-277)next_pp_rank(279-283)prev_cp_rank(294-298)next_cp_rank(300-304)Mapping(361-540)rank(199-200)rank(203-210)
tensorrt_llm/mapping.py (2)
tensorrt_llm/_torch/device_mesh.py (6)
cp_rank(84-86)rank(36-37)pp_rank(80-81)tp_group(90-91)pp_group(94-95)tp_rank(76-77)tensorrt_llm/_torch/distributed/communicator.py (7)
cp_rank(68-69)rank(40-41)rank(451-452)tp_size(64-65)pp_rank(76-77)tp_rank(72-73)pp_size(60-61)
⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (1)
- GitHub Check: Pre-commit Check
🔇 Additional comments (11)
tests/integration/test_lists/qa/llm_function_core.txt (1)
543-548: Helix DeepSeekV3Lite accuracy variants correctly scoped to pp1tp2cp2The new
test_auto_dtype_with_helix[...]entries explicitly encode thepp1tp2cp2configuration, matching the updated disaggregated‑serving test parametrization and the GSM8K regression this PR targets. Duplication in this QA list is fine given the test‑DB/waives separation.
Based on learnings, duplication across test lists is intentional.tensorrt_llm/_torch/device_mesh.py (1)
121-132: Device mesh dim order matches new TP/CP rank layoutDefining the mesh as
[pp, tp]and, whenmoe_ep_size <= 1, appending acpdimension of sizecp_sizeyields a[pp, tp, cp]layout consistent with the global rank formula used in the MPI mapping (pp outer, cp innermost). This keeps CP ranks contiguous and TP ranks interleaved with stridecp_sizeacross both orchestrators.cpp/tensorrt_llm/executor/cache_transmission/cacheSplitConcat.cu (1)
110-113: TargetRanksInfoForDP now yields CP‑consecutive, TP‑interleaved rank listsDeriving
selfCPRank = selfRank % selfCPNumselfTPRank = (selfRank % (selfTPNum * selfCPNum)) / selfCPNumis the correct inverse of
rank = pp * (tp * cp) + tp * cp + cp. The updated CP‑domain logic and the nested loops
for cp in [peerCPRankStart, peerCPRankEnd)for tp in [peerTPRankStart, peerTPRankEnd)for pp in [peerPPRankStart, peerPPRankEnd)combined with
irank = pp * (peerTPNum * peerCPNum) + tp * peerCPNum + cpproducemDomainPPSize * mDomainTPSize * mDomainCPSizeranks with CP contiguous and TP interleaved at stridepeerCPNum, matching the new mapping and cache‑split expectations.No correctness issues spotted in the new math.
Also applies to: 207-216
tensorrt_llm/mapping.py (2)
294-305: CP navigation and docs now match CP‑consecutive layout
prev_cp_rank/next_cp_ranknow assume CP ranks are stored consecutively within each (pp, tp) tile, wrapping by ±cp_sizeinside that tile. This matches the updated examples (CP groups as contiguous ranges, TP groups as interleaved) and the new group construction logic, so CP neighbor traversal is locally consistent with the underlying layout. Forcp_size == 1these methods naturally degenerate to self, which is reasonable.Also applies to: 379-389, 438-448
551-573: MpiTopology TP/CP rank decomposition and groups are internally consistent
tp_rank = (rank % (tp_size * cp_size)) // cp_size,cp_rank = rank % cp_size, andpp_rank = rank // (tp_size * cp_size)are the exact inverse ofrank = pp * (tp * cp) + tp * cp + cp._init_parallel_groups:
pp_groups: fixed (tp,cp) over all pp ranks;cp_groups: for each (pp, tp),cp_sizeconsecutive ranks;tp_groups: for each (pp, cp), TP ranks interleaved with stridecp_size.The
tp_group,pp_group, andcp_groupindex formulas (pp_rank * cp_size + cp_rank,tp_rank * cp_size + cp_rank,pp_rank * tp_size + tp_rank) align exactly with how the lists are populated. This makes the MPI mapping’s TP/CP grouping semantics match the new CP‑first/TP‑stride layout used elsewhere in the PR.Also applies to: 567-569, 599-613
tests/integration/test_lists/test-db/l0_dgx_b200.yml (1)
69-69: LGTM! Test entries align with the expanded HELIX parameterization.The new test entries correctly reference the
pp1tp2cp2configuration from the parametrized test, with appropriate 8-GPU requirements and 60-minute timeouts. The split offifoto pre_merge andncclto post_merge provides balanced CI coverage.Also applies to: 96-96
tests/unittest/others/test_mapping.py (2)
60-62: LGTM! Updated expectations correctly reflect the new CP-consecutive grouping.For
Mapping(world_size=8, rank=3, tp_size=2, pp_size=2, cp_size=2):
tp_group=[1, 3]— TP ranks now interleaved with stridecp_size=2.cp_group=[2, 3]— CP ranks are now consecutive.prev_cp_rank()=2andnext_cp_rank()=2correctly wrap within the consecutive CP group.This aligns with the PR objective of making CP ranks consecutive so that when repurposed as TP,
o_projreceives correct weights.Also applies to: 69-70
73-83: LGTM! Expectations for the 16-rank scenario correctly validate the new grouping.For
Mapping(world_size=16, rank=9, tp_size=2, pp_size=2, cp_size=4):
tp_group=[9, 13]— TP ranks at stride 4 (cp_size).cp_group=[8, 9, 10, 11]— CP ranks are consecutive.is_first_cp_rank()=False— rank 9 iscp_rank=1, not 0.prev_cp_rank()=8,next_cp_rank()=10— correct consecutive navigation within the CP group.is_last_pp_rank()=True— rank 9 ispp_rank=1, which equalspp_size - 1.prev_pp_rank()=1,next_pp_rank()=1— both wrap to rank 1 (same PP group).tensorrt_llm/models/modeling_utils.py (1)
742-747: LGTM! The rank remapping formula correctly handles the new CP-first grouping.The updated formula:
rank = (rank % (tp_size * cp_size)) // cp_size + (rank // (tp_size * cp_size)) * tp_sizeCorrectly maps CP ranks to their corresponding checkpoint files. Since different CP ranks share the same weights, they should load from the same
rank{n}.safetensorsfile. For example, withtp_size=2, cp_size=2:
- Ranks 0 and 1 (different
cp_rank, sametp_rank=0) both map torank0.safetensors.- Ranks 2 and 3 (different
cp_rank, sametp_rank=1) both map torank1.safetensors.The comment update from
"tp_cp_pp rank"to"cp_tp_pp rank"accurately reflects the new rank decomposition order.tests/integration/defs/accuracy/test_disaggregated_serving.py (2)
874-877: LGTM! Well-structured parameterization for HELIX CP/TP configurations.The new parameterization covers three key configurations that exercise the TP-CP grouping fix:
pp1tp1cp4: Pure CP parallelism (CP=4 repurposed as TP for expert parallel)pp1tp2cp2: Mixed TP/CP (the primary fix case foro_projweight distribution)pp2tp1cp2: PP + CP combinationThe
gen_ep = gen_tp * gen_cpcalculation correctly computes the MOE expert parallel size when CP ranks are repurposed as TP ranks.GPU requirements check out: ctx (4 GPUs) + gen (4 GPUs for all configs) = 8 GPUs total, matching the
@pytest.mark.skip_less_device(8)decorator.Also applies to: 894-897
906-906: Verify the context server TP size increase is intentional.The
ctx_server_config["tensor_parallel_size"]was increased from 2 to 4. This means the context server now consumes 4 GPUs instead of 2. While this works with the 8-GPU requirement (4 ctx + 4 gen), it reduces the headroom for testing additional configurations.Is this increase intentional, or should the context server remain at TP=2 to provide flexibility?
Also applies to: 918-921
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
2 times, most recently
from
c229c87 to
872167b
Compare
|
/bot run --disable-fail-fast |
|
PR_Github #30216 [ run ] triggered by Bot. Commit: |
|
PR_Github #30216 [ run ] completed with state
|
|
/bot run --disable-fail-fast |
|
PR_Github #30265 [ run ] triggered by Bot. Commit: |
|
/bot run --disable-fail-fast |
|
PR_Github #30285 [ run ] triggered by Bot. Commit: |
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
from
fe70dd1 to
edde143
Compare
|
/bot run --disable-fail-fast |
|
PR_Github #30290 [ run ] triggered by Bot. Commit: |
|
PR_Github #30290 [ run ] completed with state
|
|
/bot run --disable-fail-fast |
|
PR_Github #30299 [ run ] triggered by Bot. Commit: |
|
PR_Github #30299 [ run ] completed with state
|
|
/bot run --disable-fail-fast |
|
PR_Github #30310 [ run ] triggered by Bot. Commit: |
|
PR_Github #30310 [ run ] completed with state
|
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
from
17fc5d4 to
41aba32
Compare
|
/bot run --disable-fail-fast |
|
PR_Github #30323 [ run ] triggered by Bot. Commit: |
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
from
7577996 to
4e971dc
Compare
|
PR_Github #30323 [ run ] completed with state
|
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
from
4e971dc to
896a9f3
Compare
|
/bot run --disable-fail-fast |
|
PR_Github #30349 [ run ] triggered by Bot. Commit: |
|
PR_Github #30349 [ run ] completed with state
|
Signed-off-by: Balaram Buddharaju <[email protected]>
Signed-off-by: Balaram Buddharaju <[email protected]>
Signed-off-by: Balaram Buddharaju <[email protected]>
$ pytest tests/integration/defs/examples/test_ray.py::test_llm_inference_distributed_ray -s -v Signed-off-by: Balaram Buddharaju <[email protected]>
Signed-off-by: Balaram Buddharaju <[email protected]>
brb-nv
force-pushed
the
user/brb/alter-tp-cp-order
branch
from
896a9f3 to
168255a
Compare
|
/bot run --disable-fail-fast |
|
PR_Github #30351 [ run ] triggered by Bot. Commit: |
|
PR_Github #30351 [ run ] completed with state
|
3 participants
Description
This MR fixes poor accuracy on GSM8K accuracy benchmark when Helix CP is used along with TP on gen server.
Background:
o_projpart of attention layer.Root cause:
o_projbut there's an issue in the order of these ranks because CP ranks are interleaved.Fix:
cp_size) before repurposing.o_projwill receive the right weights.Test Coverage
PR Checklist
Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
Any new dependencies have been scanned for license and vulnerabilities
CODEOWNERS updated if ownership changes
Documentation updated as needed
Update tava architecture diagram if there is a significant design change in PR.
The reviewers assigned automatically/manually are appropriate for the PR.
Please check this after reviewing the above items as appropriate for this PR.
GitHub Bot Help
/bot [-h] ['run', 'kill', 'skip', 'reuse-pipeline'] ...Provide a user friendly way for developers to interact with a Jenkins server.
Run
/bot [-h|--help]to print this help message.See details below for each supported subcommand.
Details
run [--reuse-test (optional)pipeline-id --disable-fail-fast --skip-test --stage-list "A10-PyTorch-1, xxx" --gpu-type "A30, H100_PCIe" --test-backend "pytorch, cpp" --add-multi-gpu-test --only-multi-gpu-test --disable-multi-gpu-test --post-merge --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx" --detailed-log --debug(experimental)]Launch build/test pipelines. All previously running jobs will be killed.
--reuse-test (optional)pipeline-id(OPTIONAL) : Allow the new pipeline to reuse build artifacts and skip successful test stages from a specified pipeline or the last pipeline if no pipeline-id is indicated. If the Git commit ID has changed, this option will be always ignored. The DEFAULT behavior of the bot is to reuse build artifacts and successful test results from the last pipeline.--disable-reuse-test(OPTIONAL) : Explicitly prevent the pipeline from reusing build artifacts and skipping successful test stages from a previous pipeline. Ensure that all builds and tests are run regardless of previous successes.--disable-fail-fast(OPTIONAL) : Disable fail fast on build/tests/infra failures.--skip-test(OPTIONAL) : Skip all test stages, but still run build stages, package stages and sanity check stages. Note: Does NOT update GitHub check status.--stage-list "A10-PyTorch-1, xxx"(OPTIONAL) : Only run the specified test stages. Examples: "A10-PyTorch-1, xxx". Note: Does NOT update GitHub check status.--gpu-type "A30, H100_PCIe"(OPTIONAL) : Only run the test stages on the specified GPU types. Examples: "A30, H100_PCIe". Note: Does NOT update GitHub check status.--test-backend "pytorch, cpp"(OPTIONAL) : Skip test stages which don't match the specified backends. Only support [pytorch, cpp, tensorrt, triton]. Examples: "pytorch, cpp" (does not run test stages with tensorrt or triton backend). Note: Does NOT update GitHub pipeline status.--only-multi-gpu-test(OPTIONAL) : Only run the multi-GPU tests. Note: Does NOT update GitHub check status.--disable-multi-gpu-test(OPTIONAL) : Disable the multi-GPU tests. Note: Does NOT update GitHub check status.--add-multi-gpu-test(OPTIONAL) : Force run the multi-GPU tests in addition to running L0 pre-merge pipeline.--post-merge(OPTIONAL) : Run the L0 post-merge pipeline instead of the ordinary L0 pre-merge pipeline.--extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx"(OPTIONAL) : Run the ordinary L0 pre-merge pipeline and specified test stages. Examples: --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx".--detailed-log(OPTIONAL) : Enable flushing out all logs to the Jenkins console. This will significantly increase the log volume and may slow down the job.--debug(OPTIONAL) : Experimental feature. Enable access to the CI container for debugging purpose. Note: Specify exactly one stage in thestage-listparameter to access the appropriate container environment. Note: Does NOT update GitHub check status.For guidance on mapping tests to stage names, see
docs/source/reference/ci-overview.mdand the
scripts/test_to_stage_mapping.pyhelper.kill
killKill all running builds associated with pull request.
skip
skip --comment COMMENTSkip testing for latest commit on pull request.
--comment "Reason for skipping build/test"is required. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.reuse-pipeline
reuse-pipelineReuse a previous pipeline to validate current commit. This action will also kill all currently running builds associated with the pull request. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.
Summary by CodeRabbit
Bug Fixes
Tests
✏️ Tip: You can customize this high-level summary in your review settings.