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@MrGeva MrGeva commented Nov 4, 2025

Summary by CodeRabbit

  • New Features
    • Added symmetric memory all-reduce acceleration for H100+ GPUs to improve distributed training performance
    • Introduced SYMM_MEM strategy option for all-reduce operations
    • Updated AUTO strategy to prioritize symmetric memory acceleration when available on compatible hardware

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@MrGeva MrGeva requested a review from a team as a code owner November 4, 2025 19:28
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📝 Walkthrough

Walkthrough

Introduces symmetric memory-based AllReduce support for H100+ GPUs via a new SymmetricMemoryAllReduce class. Integrates the implementation into the existing AllReduce operator with AUTO strategy preference ordering (SYMM_MEM → MNNVL → NCCL). Adds SYMM_MEM enum value to AllReduceStrategy.

Changes

Cohort / File(s) Summary
Symmetric Memory AllReduce Implementation
tensorrt_llm/_torch/distributed/symm_mem_allreduce.py
New file. Implements SymmetricMemoryAllReduce class with PyTorch symmetric memory support detection, device capability validation (SM version), symmetric memory buffer allocation, process group establishment, and dual all-reduce paths (multimem-enabled vs. fallback). Includes should_use_symm_mem() validation and forward() execution with graceful degradation and comprehensive logging.
AllReduce Operator Integration
tensorrt_llm/_torch/distributed/ops.py
Added SymmetricMemoryAllReduce import. Extended AllReduce class with new symm_mem_allreduce field (initialized to None). Initialization logic attempts to instantiate SymmetricMemoryAllReduce when strategy is AUTO or SYMM_MEM, with try/except and logging. Forward path prioritizes symmetric memory execution (when fusion_op is NONE and symm_mem_allreduce available) before existing MNNVL handling. Updated docstring and fallback strategy logic to reflect SYMM_MEM ordering.
AllReduceStrategy Enum
tensorrt_llm/functional.py
Added SYMM_MEM = 9 enum member to AllReduceStrategy IntEnum, documented as "PyTorch symmetric memory with MULTIMEM (H100+)".

Sequence Diagrams

sequenceDiagram
    participant User
    participant AllReduce
    participant SymmMemAR as SymmetricMemoryAllReduce
    participant MNNVL
    participant NCCL
    
    User->>AllReduce: forward(input)
    
    alt fusion_op is NONE and symm_mem_allreduce available
        AllReduce->>SymmMemAR: forward(input)
        SymmMemAR->>SymmMemAR: should_use_symm_mem(input)?
        alt tensor compatible
            SymmMemAR->>SymmMemAR: copy to symm_mem buffer
            SymmMemAR->>SymmMemAR: multimem_all_reduce_ or fallback
            SymmMemAR->>SymmMemAR: copy result to output
            SymmMemAR-->>AllReduce: return output
        else tensor incompatible
            SymmMemAR-->>AllReduce: return None
        end
    end
    
    alt symm_mem_allreduce returned output
        AllReduce-->>User: return output (early exit)
    else symm_mem_allreduce unavailable or returned None
        alt strategy is MNNVL
            AllReduce->>MNNVL: forward(input)
            MNNVL-->>AllReduce: return output
        else strategy is AUTO or fallback
            AllReduce->>NCCL: forward(input)
            NCCL-->>AllReduce: return output
        end
        AllReduce-->>User: return output
    end
Loading
sequenceDiagram
    participant Init as Initialization
    participant PyTorch
    participant Device
    participant PG as ProcessGroup
    participant SymmMem as Symmetric Memory
    
    Init->>Init: Check PyTorch symm_mem availability
    alt available
        Init->>Device: Detect SM version & capability
        alt H100+ (SM >= threshold)
            Init->>Init: Validate world_size support
            alt valid
                Init->>PG: Create/use TP process group
                Init->>SymmMem: Allocate buffer (dtype-sized)
                Init->>SymmMem: Create rendezvous handle
                Init->>Init: Determine use_multimem capability
                Init-->>Init: SymmetricMemoryAllReduce ready ✓
            else invalid
                Init-->>Init: Disabled (unsupported world_size)
            end
        else older GPU
            Init-->>Init: Disabled (insufficient capability)
        end
    else unavailable
        Init-->>Init: Disabled (PyTorch support missing)
    end
Loading

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~20 minutes

  • symm_mem_allreduce.py (new file): Requires careful review of initialization logic (device capability detection, buffer allocation, algorithm selection), error handling patterns, and forward path implementation with multimem vs. fallback branching.
  • ops.py (integration): Verify correct initialization timing, integration order in forward path (priority before MNNVL), and fallback strategy logic consistency.
  • functional.py (enum): Trivial change, minimal review needed.
  • Key areas: Device capability thresholds, symmetric memory buffer sizing constraints, process group creation safety, and interaction between fusion_op check and early exit logic.

Pre-merge checks and finishing touches

❌ Failed checks (1 warning)
Check name Status Explanation Resolution
Description check ⚠️ Warning The pull request description is incomplete. The PR template sections for Description and Test Coverage are empty with only placeholder comments present. Fill in the Description section explaining what the symmetric memory AllReduce strategy is and why it's needed. Add Test Coverage section listing relevant tests that validate the new functionality.
✅ Passed checks (1 passed)
Check name Status Explanation
Title check ✅ Passed The PR title accurately describes the main change: adding a symmetric memory AllReduce strategy. It correctly identifies the primary feature addition across multiple files (new SymmetricMemoryAllReduce class, new enum member, and integration into AllReduce ops).
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Actionable comments posted: 1

📜 Review details

Configuration used: Path: .coderabbit.yaml

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 70e4d72 and 3192b19.

📒 Files selected for processing (3)
  • tensorrt_llm/_torch/distributed/ops.py (5 hunks)
  • tensorrt_llm/_torch/distributed/symm_mem_allreduce.py (1 hunks)
  • tensorrt_llm/functional.py (1 hunks)
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**/*.{h,hpp,hh,hxx,cpp,cxx,cc,cu,cuh,py}

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Files:

  • tensorrt_llm/_torch/distributed/symm_mem_allreduce.py
  • tensorrt_llm/_torch/distributed/ops.py
  • tensorrt_llm/functional.py
**/*.{cpp,cxx,cc,h,hpp,hh,hxx,cu,cuh,py}

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🧠 Learnings (8)
📚 Learning: 2025-08-14T06:36:40.701Z
Learnt from: timlee0212
Repo: NVIDIA/TensorRT-LLM PR: 6886
File: tensorrt_llm/_torch/models/modeling_deepseekv3.py:0-0
Timestamp: 2025-08-14T06:36:40.701Z
Learning: In DeepSeek V3 model (tensorrt_llm/_torch/models/modeling_deepseekv3.py), the disagreement between AllReduce.__init__ guard and _compute_mlp_tp_size logic for MNNVL usage is expected by design. The AllReduce component and MLP TP-size computation intentionally use different criteria for MNNVL availability decisions.

Applied to files:

  • tensorrt_llm/_torch/distributed/symm_mem_allreduce.py
  • tensorrt_llm/_torch/distributed/ops.py
📚 Learning: 2025-09-24T03:31:28.908Z
Learnt from: tongyuantongyu
Repo: NVIDIA/TensorRT-LLM PR: 7520
File: tensorrt_llm/_torch/pyexecutor/resource_manager.py:605-613
Timestamp: 2025-09-24T03:31:28.908Z
Learning: In TensorRT-LLM Ray orchestrator mode, ProcessGroups are initialized with both Gloo and NCCL backends (e.g., "cuda:nccl,cpu:gloo"), allowing PyTorch distributed to automatically route CPU tensors through Gloo and GPU tensors through NCCL. This eliminates the need for manual device placement when performing allreduce operations on base types.

Applied to files:

  • tensorrt_llm/_torch/distributed/symm_mem_allreduce.py
  • tensorrt_llm/_torch/distributed/ops.py
📚 Learning: 2025-10-13T19:45:03.518Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: tests/unittest/_torch/multi_gpu/test_nccl_device.py:138-149
Timestamp: 2025-10-13T19:45:03.518Z
Learning: In test_nccl_device.py, the NCCL device AllReduce implementation compares the entire residual tensor on each rank, unlike the UB implementation which compares per-rank chunks. The residual chunking calculations in the test are intentionally overridden to reflect this design difference.

Applied to files:

  • tensorrt_llm/_torch/distributed/symm_mem_allreduce.py
  • tensorrt_llm/_torch/distributed/ops.py
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device allreduce implementation (cpp/tensorrt_llm/thop/allreduceOp.cpp), the goto pattern in runNCCLAllReduceDeviceFusion is intentionally used for future extensibility, allowing multiple switch cases to fallback to the default handler. While not aesthetically ideal, this pattern supports adding more fusion cases later that can reuse the same fallback logic.

Applied to files:

  • tensorrt_llm/_torch/distributed/symm_mem_allreduce.py
  • tensorrt_llm/_torch/distributed/ops.py
  • tensorrt_llm/functional.py
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device implementation, NCCL version 2.28+ requirements are handled at runtime in the nccl_device/config layer rather than with compile-time guards. This allows the allreduceOp to remain version-agnostic and delegates version compatibility validation to the appropriate lower-level components that can gracefully handle unsupported configurations.

Applied to files:

  • tensorrt_llm/_torch/distributed/symm_mem_allreduce.py
  • tensorrt_llm/_torch/distributed/ops.py
📚 Learning: 2025-09-02T13:42:44.885Z
Learnt from: pcastonguay
Repo: NVIDIA/TensorRT-LLM PR: 7455
File: tensorrt_llm/_torch/pyexecutor/py_executor.py:1852-1860
Timestamp: 2025-09-02T13:42:44.885Z
Learning: In MPI communication within TensorRT-LLM pipeline parallelism, different communication types (tokens, logits, termination sync) must use disjoint tag namespaces to avoid message routing collisions when using the same source/destination patterns.

Applied to files:

  • tensorrt_llm/_torch/distributed/ops.py
📚 Learning: 2025-09-16T09:30:09.716Z
Learnt from: tongyuantongyu
Repo: NVIDIA/TensorRT-LLM PR: 7763
File: cpp/tensorrt_llm/CMakeLists.txt:297-301
Timestamp: 2025-09-16T09:30:09.716Z
Learning: In the TensorRT-LLM project, NCCL libraries are loaded earlier by PyTorch libraries or the bindings library, so the main shared library doesn't need NCCL paths in its RPATH - the libraries will already be available in the process address space when needed.

Applied to files:

  • tensorrt_llm/_torch/distributed/ops.py
📚 Learning: 2025-09-23T14:58:05.372Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:42-49
Timestamp: 2025-09-23T14:58:05.372Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/), the token partitioning intentionally uses ceil-like distribution (same token_per_rank for all ranks) to ensure all ranks launch the same number of blocks. This is required for optimal NCCL device API barrier performance, even though it may launch extra blocks for non-existent tokens on later ranks. Runtime bounds checking in the kernel (blockID validation) handles the overshoot cases.

Applied to files:

  • tensorrt_llm/_torch/distributed/ops.py
🧬 Code graph analysis (2)
tensorrt_llm/_torch/distributed/symm_mem_allreduce.py (2)
tensorrt_llm/mapping.py (1)
  • Mapping (336-493)
tensorrt_llm/_torch/distributed/ops.py (3)
  • forward (432-503)
  • forward (621-709)
  • forward (747-800)
tensorrt_llm/_torch/distributed/ops.py (2)
tensorrt_llm/_torch/distributed/symm_mem_allreduce.py (1)
  • SymmetricMemoryAllReduce (30-221)
tensorrt_llm/functional.py (6)
  • AllReduceStrategy (3876-3886)
  • dtype (255-259)
  • dtype (262-267)
  • shape (270-274)
  • shape (277-282)
  • shape (2056-2096)
🪛 Ruff (0.14.3)
tensorrt_llm/_torch/distributed/symm_mem_allreduce.py

45-48: Mutable class attributes should be annotated with typing.ClassVar

(RUF012)


51-61: Mutable class attributes should be annotated with typing.ClassVar

(RUF012)


160-160: Do not catch blind exception: Exception

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tensorrt_llm/_torch/distributed/ops.py

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🔇 Additional comments (1)
tensorrt_llm/functional.py (1)

3886-3887: Enum addition verified—existing TRT safeguards already in place.

The SYMM_MEM enum addition (lines 3886–3887) is safe and properly commented. The TRT path is already protected: the distributed/ops.py layer (lines 679–682) remaps SYMM_MEM to AUTO before the TRT allreduceOp plugin, and the torch runtime correctly handles it via SymmetricMemoryAllReduce (line 578).

The suggested guard in allreduce() is architecturally unnecessary—the safeguard is appropriately delegated to the lower-level distributed layer, consistent with TensorRT-LLM's runtime-handling pattern. No critical issues detected.

@MrGeva MrGeva changed the title Added symetric memory AllReduce strategy Draft - DON'T REVIEW - Added symetric memory AllReduce strategy Nov 4, 2025
@MrGeva MrGeva changed the title Draft - DON'T REVIEW - Added symetric memory AllReduce strategy Added symetric memory AllReduce strategy Nov 4, 2025
@MrGeva MrGeva changed the title Added symetric memory AllReduce strategy [#8921][feat] Added symetric memory AllReduce strategy Nov 4, 2025
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MrGeva commented Nov 4, 2025

/bot run

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PR_Github #23543 [ run ] triggered by Bot. Commit: 3cb8ff4

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PR_Github #23543 [ run ] completed with state SUCCESS. Commit: 3cb8ff4
/LLM/main/L0_MergeRequest_PR pipeline #17718 completed with status: 'FAILURE'

Signed-off-by: Eran Geva <[email protected]>
Signed-off-by: Eran Geva <[email protected]>
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MrGeva commented Nov 5, 2025

/bot run

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PR_Github #23584 [ run ] triggered by Bot. Commit: 668b514

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PR_Github #23584 [ run ] completed with state SUCCESS. Commit: 668b514
/LLM/main/L0_MergeRequest_PR pipeline #17746 completed with status: 'FAILURE'

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MrGeva commented Nov 5, 2025

/bot run

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PR_Github #23625 [ run ] triggered by Bot. Commit: ef29244

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PR_Github #23625 [ run ] completed with state SUCCESS. Commit: ef29244
/LLM/main/L0_MergeRequest_PR pipeline #17777 completed with status: 'FAILURE'

@MrGeva MrGeva requested a review from a team as a code owner November 5, 2025 16:47
@MrGeva MrGeva requested a review from nvchenghaoz November 5, 2025 16:47
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MrGeva commented Nov 5, 2025

/bot run

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PR_Github #23663 [ run ] triggered by Bot. Commit: 511139f

# Use SYMM_MEM strategy (tries symmetric memory first, falls back to AUTO if needed)
_allreduce_cache[cache_key] = AllReduce(
mapping=p_config, strategy=AllReduceStrategy.AUTO, dtype=tensor.dtype
mapping=p_config, strategy=AllReduceStrategy.SYMM_MEM, dtype=tensor.dtype
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@MrGeva : we should make this configurable and users should be able to specify the choice through inference optimizer config. Would you be able to take on the task of plumbing the AllReduceStrategy from the top level default.yaml -> sharding transformation -> inserting the all reduce op with the specified strategy?

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