Acceptance Test Project
This page describes how to set up the NetFPGA-SUME board and run the initial Acceptance Test. The Acceptance Test verifies that your board is working correctly. You should run the Acceptance Test before attempting any development with a new NetFPGA-SUME board. If the tests indicate a problem with your board, return it immediately to your distributor.
The Acceptance Test is performed by the NetFPGA-SUME’s Virtex7 FPGA. The status of the tests is displayed using a python-based GUI. An Acceptance Test suite, containing the hw design along with supporting software, is provided in the NetFPGA-SUME github repository under the projects/acceptance_test/ subdirectory.
By default, the Acceptance Test checks on board interfaces and the SFP+ interfaces. The Acceptance Test provides cover for all interfaces, however some interfaces require additional hardware for testing. We provide more information about this below.
Note : Please make sure that you have followed the installation procedure as mentioned in the Reference Operating System Setup Guide before running the test
The NetFPGA-10G Production Test is run in Server Mode, wherein the NetFPGA-SUME board is installed as PCIe expansion card in a host PC, allowing most major on-board systems to be verified.
- Clone the NetFPGA SUME development repository using the following command
git clone https://github.com/NetFPGA/NetFPGA-SUME-live.git
- Source the Xilinx Vivado tools
source cd /{installation_directory}/Vivado/2014.4/settings64.sh
-
Edit the
NetFPGA-SUME-live/tools/settings.shfiles to export paths based on your installation directory. -
Source the updated settings.sh
source NetFPGA-SUME-live/tools/settings.sh
- Go to the acceptance project folder
cd NetFPGA-SUME-live/projects/acceptance_test/
- Build the IP cores for the acceptance test by running the following command
make cores
- Then you can run the Test GUI by running
make test
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The NetFPGA-SUME Acceptance test GUI will pop up. Choose the right serial interface as shown below
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Click the start button (as shown below) and the GUI will show all the tests available
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You can click the "Run Auto Test" button to start the the default test. If any of the bit files are missing, the test will automatically generate them.
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Once the default tests are run, the status of the tests can be viewed under the Results section.
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Acceptance tests The acceptance tests have a set of default tests and some optional tests.
Acceptance Test
├── Default Test
│ └── DDR3 A/B Tests
│ └── QDR A/B/C Tests
│ └── 10G Ethernet Loopback Test
│ └── CPLD and Flash Test
├── Optional Test
│ └── PCI-E Loopback Test
│ └── FMC GTX Loopback Test
│ └── QTH GTX Loopback Test
│ └── GPIO/IIC/UART General Test
│ └── SATA GTX Loopback Test
- The default tests include testing the following projects:
├── Default Test
│ └── DDR3 A/B Tests
│ └── QDR A/B/C Tests
│ └── 10G Ethernet Loopback Test
│ └── CPLD and Flash Test
For the 10G Ethernet Loopback Test requires fibers and 10G SFP+ transceivers. The test configuration should be connected in a port to port loopback mode (0-1,2-3).
**Note: While running the memory tests (DDR's and QDR's), some test may fail at the first instant. Try running another time. **
- Optional tests (covered by the Acceptance Test) require dedicated hardware and cables. Some of the hardware required can be easily acquired by users (e.g. SD card or crossed SATA cable), other adapters are currently not widely available, though we hope to make their design available online. Information about cables is provided in the next section.
├── Optional Test
│ └── PCI-E Loopback Test
│ └── FMC GTX Loopback Test
│ └── QTH GTX Loopback Test
│ └── GPIO/IIC/UART General Test
│ └── SATA GTX Loopback Test
The above figure shows the standalone acceptance test along with the loopback boards and other test interfaces.
This section provides further details (like interface configuration details, board requirements etc) about the acceptance tests. The following section also illustrates how to run the tests in the non-gui mode (by directly calling the make files).
The tests included in the acceptance_test project are shown as follows:
- DDR3 A/B Tests
- QDR A/B/C Tests
- 10G Ethernet Loopback Test (SFP+ transceivers and fibers are required)
(Additional tests)
- PCI-E Loopback Test (PCI-E Loopback Board required)
- FMC GTX Loopback Test (FMC Loopback Board required)
- QTH GTX Loopback Test (QTH Loopback Board required)
- GPIO/IIC/UART General Test (FMC Looopback Board, Pmod Loopback Test Fixture required)
- SATA GTX Loopback Test (SATA III Cross-over Cable required)
Note: Following tests are not used in the GUI framework
- PCI-E Gen3 x8 In-box R/W Test (Host driver included)
- FMC Aurora Loopback Test (FMC Loopback Board required)
- FMC iBert Test (FMC Loopback Board required)
- QTH Aurora Loopback Test (QTH Loopback Board required)
- QTH iBert Test (QTH Loopback Board required)
In this documentation, instructions on how to compile, run and debug each test are provided. The configuration of each interface are listed in each test section. This project can serve as a guidance on how to configure and test the interface.
Note: As the project is still under development, the contents of this page will be populated gradually
DDR3 A/B Test is built based on Xilinx 7 Series MIG Example Design with a Uart interface to read the status of the test. Logic analyzer core is inserted to provide more detailed debugging information to the users if the test fails.
| Parameter Name | Value | Coment |
|---|---|---|
| Clock Period | 1225 ps | 849.62MHz, 1700MTps, Please Refer to Xilinx AR61853 |
| DDR Type | DDR3 SODIMM | |
| Part No | MT8KTF51264Hz-1G9 | |
| Voltage | 1.5V | |
| Axi Data Width | 128 | |
| Arbitrition | RD_PRI_REG | |
| Narror Burst Support | Disabled | |
| Input Clock | 4288 ps | 233.209MHz |
| Read Burst | Sequential | |
| Output Drive Impedance | RZQ/7 | |
| ODT | RZQ/6 | |
| CS | Enabled | |
| Reset Polarity | Active High | |
| IO Power Reduction | ON |
Under Acceptance Test folder, run
$ make ddr3A
$ make ddr3B
The script will generate the hardware of the project under folder hw/project/nf_sume_ddr3A_example and hw/project/nf_sume_ddr3B_example respectively. The synthesize and implementation procedure of both projects will start automatically. After generating the bitfiles, the hardware profile will be exported to sw/nf_sume_ddr3A, and a SDK project will be created there for microblaze software compilation. The generated elf file will be linked back to the hardware project and a compressed bitfile will be generated and copied to bitfiles folder.
You can open the project in Vivado, connect NetFPGA-SUME board to your PC and download the bitfile to the board. Please refer to Xilinx document UG586: Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v2.3 for detailed explanation of debugging signals. LD0 is used to indicate the presence of DDR3 233MHz reference clock, and LD1 is used to indicate whether DDR3 calibration is successfully or not.
QDR A/B/C Test is built based on Xilinx 7 Series MIG Example Design with a Uart interface to read the status of the test. Logic analyzer core is inserted to provide more detailed debugging information to the users if the test fails.
| Parameter Name | Value | Coment |
|---|---|---|
| Clock Period | 2000 ps | 500MHz |
| DDR Type | Components-BL4 | |
| Part No | CY7C25652KV18-500BZC | |
| Fixed Latency | Disabled | |
| Input Clock | 5000 ps | 200MHz |
| Reset Polarity | Active High | |
| DCI for Data and Read Clocks | Enabled |
Under Acceptance Test folder, run
$ make qdrA qdrB qdrC
The script will generate the hardware of the project under folder hw/project/nf_sume_qdrA_example, hw/project/nf_sume_qdrB_example and hw/project/nf_sume_qdrC_example respectively. The synthesize and implementation procedure of both projects will start automatically. After generating the bitfiles, the hardware profile will be exported to sw/nf_sume_qdrA, sw/nf_sume_qdrB and sw/nf_sume_qdrC, and a SDK project will be created there for microblaze software compilation. The generated elf file will be linked back to the hardware project and a compressed bitfile will be generated and copied to bitfiles folder.
You can open the project in Vivado, connect NetFPGA-SUME board to your PC and download the bitfile to the board. Please refer to Xilinx document UG586: Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v2.3 for detailed explanation of debugging signals. LD0 is used to indicate read/write data mismatch, and LD1 is used to indicate whether QDR calibration is successfully or not.
PCI-Express Gen3 x8 inbox register R/W test is bult based on Xilinx VC709 PCI-Express Reference Design (XTP237, rdf0235). Host driver and user application are provided under sw/host folder. The project utilizes Xilinx 7 Series PCI-Express Gen3 IP Core with a PCI-Express to Axi-Lite bridge to perform 32-bit word based Read/Write to Block RAM instantiated.
| Parameter Name | Value | Coment |
|---|---|---|
| Device/Port Type | PCI Express Endpoint Device | |
| PCIe Block Location | X0Y1 | |
| Reference Clock Frequency | 100MHz | |
| Xilinx Development Board | None | |
| Silicon Revision | Production | |
| Number of Lanes | x8 | |
| Maximum Link Speed | 8.0GT/s | |
| AXI-ST Interface Width | 256-bit | |
| AXI-ST Interface Frequency | 250MHz | |
| AXI-ST Alignment Mode | DWORD Aligned | |
| Tandem Configuration | None | |
| Vendor ID | 0x10EE | |
| Device ID | 0x0007 | |
| Revision ID | 0x0000 | |
| Subsystem Vendor ID | 0x10EE | |
| Subsystem ID | 0x0007 | |
| Class Code | 0x058000 | Simple Communication, General XT Compatible Controller, Interface 0 |
| Number of BARs | 2 | |
| BAR0 | Memory, 8KB | |
| BAR1 | Memory, 4KB | |
| PF0 Interrupt Pin | INTA | |
| PF0 MSI Capability Structure | Enabled | |
| Shared Logic | (None Selected) | |
| Core Interface Parameter | (None Selected) |
Under Acceptance Test folder, run
$ make pcie_g3
The script will generate the hardware of the project under folder hw/project/nf_sume_pcie_g3_example. The synthesize and implementation procedure of both projects will start automatically. A compressed bitfile will be generated and copied to bitfiles folder after the compilation.
Plug NetFPGA-SUME board into a PCI-E slot that is compatible with PCI-Express Gen3 x8. In our development environment, we uses ASUS Z87-A motherboard.
QTH iBERT test utilizes Xilinx iBERT 7-series GTH cores that exercise all 8 GTH lanes on QTH connectors at 12.5Gbps with 156.25Mhz Reference Clock. QTH Loopback board is required to run this project.
| Parameter Name | Value | Coment |
|---|---|---|
| Silicon Version | General ES/Production | |
| Protocol | Custom | |
| Line Rate | 12.5Gbps | |
| Data Width | 32 | |
| Refclk | 156.25MHz | |
| Quad Count | 2 | 8 lanes |
| Quad PLL | Checked | |
| Protocol Selection | QUAD 117/118: Custom/12.5Gbps, Others: None | |
| Refclk Selection | QUAD 117/118: MGTREFCLK0118, Others: None | |
| TXUSRCLK Source | Channel 0 | |
| System Clock Source | External | |
| System Clock IO Standard | DIFF SSTL15 | |
| System Clock P Package Pin | H19 | |
| System Clock N Package Pin | G18 | |
| System Clock Frequency | 200MHz |
Under Acceptance Test folder, run
$ make qth_ibert
The script will generate the hardware of the project under folder hw/project/nf_sume_qth_ibert_example. The synthesize and implementation procedure of both projects will start automatically. A compressed bitfile will be generated and copied to bitfiles folder after the compilation.
Plug-in QTH Loopback board, start vivado Design Suite and open project nf_sume_qth_ibert_example under folder hw/project/nf_sume_qth_ibert_example. Open Hardware Manager and start QTH iBERT Test.
QTH GT-Wizard test utilizes Xilinx 7 series FPGAs Transceiver Wizard that exercise all 8 GTH lanes on QTH connectors at 12.5Gbps with 156.25Mhz Reference Clock. QTH Loopback board (shown below) is required to run this project.
| Parameter Name | Value | Coment |
|---|---|---|
| GT Type | GTH | |
| Shared Logic | include in Example Design | |
| TX Line Rate | 12.5Gbps | |
| TX Reference Clock | 156.25MHz | |
| RX Line Rate | 12.5Gbps | |
| RX Reference Clock | 156.25MHz | |
| PLL Selection | TX/RX: QPLL | |
| GTH X1Y28 - X1Y35 | TX/RX Clock Source: REFCLK0 Q8 | |
| Vivado Lab Tools | Enabled | |
| TX External Data Width | 32 | |
| TX Encoding | 64/66 With Ext Seq Ctr | |
| TX Internal Data Width | 32 | |
| RX External Data Width | 32 | |
| RX Encoding | 64/66 | |
| RX Internal Data Width | 32 | |
| Use DRP | Disabled | |
| TX Buffer | Enabled | |
| RX BUffer | Enabled |
Under Acceptance Test folder, run
$ make qth_gtwizard
The script will generate the hardware of the project under folder hw/project/nf_sume_qth_ibert_example. The synthesize and implementation procedure of both projects will start automatically. A compressed bitfile will be generated and copied to bitfiles folder after the compilation.
Plug-in QTH Loopback board, start vivado Design Suite and open project nf_sume_qth_ibert_example under folder hw/project/nf_sume_qth_ibert_example. Open Hardware Manager and start QTH iBERT Test.
FMC iBERT test utilizes Xilinx iBERT 7-series GTH cores that exercise all 10 GTH lanes on FMC connectors at 12.5Gbps with 156.25Mhz Reference Clock. FMC Loopback board is required to run this project.
| Parameter Name | Value | Coment |
|---|---|---|
| Silicon Version | General ES/Production | |
| Protocol | Custom | |
| Line Rate | 12.5Gbps | |
| Data Width | 32 | |
| Refclk | 156.25MHz | |
| Quad Count | 3 | 12 lanes, 2 unused |
| Quad PLL | Checked | |
| Protocol Selection | QUAD 111/112/113: Custom/12.5Gbps, Others: None | |
| Refclk Selection | QUAD 111/112/113: MGTREFCLK0112, Others: None | |
| TXUSRCLK Source | Channel 0 | |
| System Clock Source | External | |
| System Clock IO Standard | DIFF SSTL15 | |
| System Clock P Package Pin | H19 | |
| System Clock N Package Pin | G18 | |
| System Clock Frequency | 200MHz |
Under Acceptance Test folder, run
$ make fmc_ibert
The script will generate the hardware of the project under folder hw/project/nf_sume_fmc_ibert_example. The synthesize and implementation procedure of both projects will start automatically. A compressed bitfile will be generated and copied to bitfiles folder after the compilation.
Plug-in FMC Loopback board, start vivado Design Suite and open project nf_sume_fmc_ibert_example under folder hw/project/nf_sume_fmc_ibert_example. Open Hardware Manager and start FMC iBERT Test.
FMC GT-Wizard test utilizes Xilinx 7 series FPGAs Transceiver Wizard that exercise all 10 GTH lanes on FMC connectors at 12.5Gbps with 156.25Mhz Reference Clock. FMC Loopback board (shown below) is required to run this project.
| Parameter Name | Value | Coment |
|---|---|---|
| GT Type | GTH | |
| Shared Logic | include in Example Design | |
| TX Line Rate | 12.5Gbps | |
| TX Reference Clock | 156.25MHz | |
| RX Line Rate | 12.5Gbps | |
| RX Reference Clock | 156.25MHz | |
| PLL Selection | TX/RX: QPLL | |
| GTH X1Y4 - X1Y13 | TX/RX Clock Source: REFCLK0 Q2 | |
| Vivado Lab Tools | Enabled | |
| TX External Data Width | 32 | |
| TX Encoding | 64/66 With Ext Seq Ctr | |
| TX Internal Data Width | 32 | |
| RX External Data Width | 32 | |
| RX Encoding | 64/66 | |
| RX Internal Data Width | 32 | |
| Use DRP | Disabled | |
| DRP Clock Frequency | 100MHz | |
| TX Buffer | Enabled | |
| RX BUffer | Enabled |
Under Acceptance Test folder, run
$ make fmc_gtwizard
The script will generate the hardware of the project under folder hw/project/nf_sume_fmc_gtwizard_example. The synthesize and implementation procedure of both projects will start automatically. A compressed bitfile will be generated and copied to bitfiles folder after the compilation.
Plug-in FMC Loopback board, start vivado Design Suite and open project nf_sume_fmc_gtwizard_example under folder hw/project/nf_sume_fmc_gtwizard_example. Open Hardware Manager and start FMC GtWizard Acceptance Test.
SATA test utilizes Xilinx 7 series FPGAs Transceiver Wizard that exercise all 2 GTH lanes on two SATA connectors at 6Gbps (SATA-III) with 150Mhz Reference Clock. SATA Crossover cable (shown below) is required to run this project.
| Parameter Name | Value | Coment |
|---|---|---|
| GT Type | GTH | |
| Shared Logic | include in Example Design | |
| TX Line Rate | 6Gbps | |
| TX Reference Clock | 150MHz | |
| RX Line Rate | 6Gbps | |
| RX Reference Clock | 150MHz | |
| PLL Selection | TX/RX: CPLL | |
| GTH X1Y24 - X1Y25 | TX/RX Clock Source: REFCLK1 Q6 | |
| Vivado Lab Tools | Enabled | |
| TX External Data Width | 16 | |
| TX Encoding | 8B/10B | |
| TX Internal Data Width | 20 | |
| RX External Data Width | 16 | |
| RX Encoding | 8B/10B | |
| RX Internal Data Width | 20 | |
| Use DRP | Disabled | |
| SATA COM Sequence | 6 Bursts/ 6 Idles | |
| TX Buffer | Enabled | |
| RX BUffer | Enabled |
Under Acceptance Test folder, run
$ make sata
The script will generate the hardware of the project under folder hw/project/nf_sume_sata_example. The synthesize and implementation procedure of both projects will start automatically. A compressed bitfile will be generated and copied to bitfiles folder after the compilation.
PCIE test utilizes Xilinx 7 series FPGAs Transceiver Wizard that exercise all 8 GTH lanes on PCIE connectors at 8Gbps (Gen-III) with 100Mhz Reference Clock. PCI-E Loopback board (shown below) is required to run this project.
| Parameter Name | Value | Coment |
|---|---|---|
| GT Type | GTH | |
| Shared Logic | include in Example Design | |
| TX Line Rate | 8Gbps | |
| TX Reference Clock | 100MHz | |
| RX Line Rate | 8Gbps | |
| RX Reference Clock | 100MHz | |
| PLL Selection | TX/RX: QPLL | |
| GTH X1Y16 - X1Y23 | TX/RX Clock Source: REFCLK1 Q5 | |
| Vivado Lab Tools | Enabled | |
| TX External Data Width | 64 | |
| TX Encoding | 64B/66B with Ext Seq Ctr | |
| TX Internal Data Width | 32 | |
| RX External Data Width | 64 | |
| RX Encoding | 64B/66B | |
| RX Internal Data Width | 32 | |
| Use DRP | Disabled | |
| TX Buffer | Enabled | |
| RX BUffer | Enabled |
Under Acceptance Test folder, run
$ make pcie
The script will generate the hardware of the project under folder hw/project/nf_sume_pcie_example. The synthesize and implementation procedure of both projects will start automatically. A compressed bitfile will be generated and copied to bitfiles folder after the compilation.
The 10g loopback test uses Xilinx 10g ethernet subsystem core. More technical details regarding the configuration of the core will be added in due course. The loopback configuration for the test is shown below.
Under Acceptance Test folder, run
$ make 10g_loopback
The GPIO/IIC/UART test the GPIO, IIC and UART peripherals. For the test we require GPIO loopback pins (shown below), micro SD card (not shown). More technical details regarding the configuration of the design will be added in due course.
Under Acceptance Test folder, run
$ make 10g_loopback