DDR3 SDRAM Performance with Xilinx MIG

DDR3 SDRAM Performance with Xilinx MIG

Throughput Measurement

I measured throughput with counting the number of app_cmd issued per one second. IOPS means the number of app_cmd issued. An average bitrate is calculated by multiplying the IOPS by data width (e.g., 512).

DRAM Throughput (Average of 300 seconds)

Order Mode : Normal

	# of BANK Machine	avg. IOPS	avg. bitrate(Gbps)
RANDOM-READ-WRITE	2	21,666,600	11.0933
RANDOM READ	2	27,194,700	13.9237
RANDOM WRITE	2	20,709,400	10.6032
RANDOM-READ-WRITE	4	38,428,400	19.6754
RANDOM READ	4	48,157,500	24.6567
RANDOM WRITE	4	32,138,000	16.4546
RANDOM-READ-WRITE	8	51,356,500	26.2945
RANDOM READ	8	73,420,300	37.5912
RANDOM WRITE	8	35,757,600	18.3079

Order Mode : Strict

	# of BANK Machine	avg. IOPS	avg. bitrate(Gbps)
RANDOM-READ-WRITE	2	21,666,600	11.0933
RANDOM READ	2	27,194,700	13.9237
RANDOM WRITE	2	20,709,500	10.6032
RANDOM-READ-WRITE	4	32,384,100	16.5807
RANDOM READ	4	42,686,500	21.8555
RANDOM WRITE	4	32,053,800	16.4116
RANDOM-READ-WRITE	8	32,902,700	16.8462
RANDOM READ	8	46,790,000	23.9565
RANDOM WRITE	8	35,461,000	18.156

Order Mode : Relaxed

	# of BANK Machine	avg. IOPS	avg. bitrate(Gbps)
RANDOM-READ-WRITE	2	21,666,500	11.0933
RANDOM READ	2	27,194,700	13.9237
RANDOM WRITE	2	20,709,500	10.6032
RANDOM-READ-WRITE	4	38,900,900	19.9173
RANDOM READ	4	48,157,600	24.6567
RANDOM WRITE	4	36,365,300	18.619
RANDOM-READ-WRITE	8	57,888,800	29.6391
RANDOM READ	8	73,420,100	37.5911
RANDOM WRITE	8	55,727,300	28.5324

Latency

Latency is measured via Xilinx MIG. Specifically, I measured DRAM latency including MIG from app_cmd issued until app_rd_valid is high.　Two types of traffic pattern are tested below.

• RANDOM READ AND WRITE: Issuing READ and WRITE CMD by turns.
• RANDOM READ : Issuing only READ CMD.

[1] Experiment Environment

Traffic Pattern	RANDOM READ and WRITE Mixes
# of BANK_MACHS	8
Reorder Mode	Relaxed
Address MAP	ROW_BANK_COLUMN
Read mode	Sequential

[1] Experiment Result with 1184131 READ CMD issued

	Clock Cycles [200MHz]	Time [nano second]
Maximum	190	950
Minimum	28	140
Avarage	53.35	266.75
Variance	237.182	1,185.91

[2] Experiment Environment

Traffic Pattern	RANDOM READ
# of BANK_MACHS	8
Reorder Mode	Relaxed
Address MAP	ROW_BANK_COLUMN
Read mode	Sequential

[2] Experiment Result with 3007311 READ CMD issued

	Clock Cycles [200MHz]	Time [nano second]
Maximum	160	800
Minimum	30	150
Avarage	50.55	252.75
Variance	131.148	655.74

Contact

Yuta Tokusashi (Keio Univ.)
[email protected]